[coreboot-gerrit] Patch merged into coreboot/master: fe74092 samus: Fix up memory SPD information

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit fe74092c4e802efbed76804fb43f0bd25a5721b2
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Oct 22 16:35:12 2013 -0700

    samus: Fix up memory SPD information
    
    The LPDDR3 memory is x32 and dual rank with 14 row bits.
    
    In addition the memory is actually elpida, even though
    they are owned by micron it is confusing to label it as such.
    
    And the ram strap options were inverted from what I expected
    so the memory table needs to be updated.
    
    Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/174121
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65)
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
    Reviewed-on: http://review.coreboot.org/6828
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>


See http://review.coreboot.org/6828 for details.

-gerrit