[coreboot-gerrit] Patch set updated for coreboot: 396845a lenovo/t530: Use native LVDS gfx init

[Edward O'Callaghan (eocallaghan@alterapraxis.com)]

Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6395

-gerrit

commit 396845a095863ef6b0999c0c2a90da9677eac07b
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date:   Tue Jul 29 14:42:26 2014 +1000

    lenovo/t530: Use native LVDS gfx init
    
    As introduced in:
    1783a3c ivybridge: LVDS gfx init.
    
    The panel on the T530 is a AUO B156HW01 V.4, 40 pin LVDS (2 ch, 6-bit).
    Tx parameters derived from datasheet table.
    
    Change-Id: I2e3b56a2a3d1ede08a704b839cc11fe6d685cf5b
    Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
 src/mainboard/lenovo/t530/Kconfig       |  6 ++++++
 src/mainboard/lenovo/t530/devicetree.cb | 10 ++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index 8e49277..c34b647 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -14,6 +14,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_RESUME
 	select HAVE_SMI_HANDLER
 	select INTEL_INT15
+	select EARLY_CBMEM_INIT
+	select VGA
+	select INTEL_EDID
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
+	select IVYBRIDGE_LVDS
 
 	# Workaround for EC/KBC IRQ1.
 	select SERIRQ_CONTINUOUS_MODE
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index 6a09004..b22d405 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -8,8 +8,14 @@ chip northbridge/intel/sandybridge
 	register "gpu_panel_power_cycle_delay" = "6"		# T7: 500ms
 	register "gpu_panel_power_up_delay" = "100"		# T1+T2: 10ms
 	register "gpu_panel_power_down_delay" = "100"		# T5+T6: 10ms
-	register "gpu_panel_power_backlight_on_delay" = "2100"	# T3: 210ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# T4: 210ms
+	register "gpu_panel_power_backlight_on_delay" = "2000"	# T3: 200ms
+	register "gpu_panel_power_backlight_off_delay" = "2000"	# T4: 200ms
+	register "gpu_use_spread_spectrum_clock" = "1"
+	register "gpu_lvds_dual_channel" = "1"
+	register "gpu_link_frequency_270_mhz" = "1"
+	register "gpu_lvds_num_lanes" = "1"
+	register "gpu_cpu_backlight" = "0x1155"
+	register "gpu_pch_backlight" = "0x11551155"
 
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989