[coreboot-gerrit] Patch merged into coreboot/master: 0650cd0 southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0650cd0bad2816886745c4a7ffe0e7a1aefb9957
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date:   Wed Feb 5 15:03:50 2014 +0100

    southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.
    
    X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash
    but address map limits this to 16MiB.
    
    Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d
    Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
    Reviewed-on: http://review.coreboot.org/5133
    Tested-by: build bot (Jenkins)
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>


See http://review.coreboot.org/5133 for details.

-gerrit