[coreboot-gerrit] New patch to review for coreboot: 81d5ea9 samus: Enable XHCI mode by default

[Isaac Christensen (isaac.christensen@se-eng.com)]

Isaac Christensen (isaac.christensen at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6908

-gerrit

commit 81d5ea9c7e13b634dfbf840608a531dfe187375c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Dec 18 10:55:48 2013 -0800

    samus: Enable XHCI mode by default
    
    - Enable xhci_default setting in devicetree
    - Enable usb_xhci_on_resume setting for PEI
    
    Change-Id: I2a3965a222ce571a2ad43f568fc2d0ecb94a77bc
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://chromium-review.googlesource.com/180673
    (cherry picked from commit c5ef875f6d148964b8ad62a3fe79916c758dbc57)
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
---
 src/mainboard/google/samus/devicetree.cb | 3 +++
 src/mainboard/google/samus/romstage.c    | 1 +
 2 files changed, 4 insertions(+)

diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb
index f848edc..12a21ec 100644
--- a/src/mainboard/google/samus/devicetree.cb
+++ b/src/mainboard/google/samus/devicetree.cb
@@ -80,6 +80,9 @@ chip northbridge/intel/haswell
 			# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
 			register "icc_clock_disable" = "0x013e0000"
 
+			# Route all USB ports to XHCI per default
+			register "xhci_default" = "1"
+
 			device pci 13.0 on end # Smart Sound Audio DSP
 			device pci 14.0 on end # USB3 XHCI
 			device pci 15.0 on end # Serial I/O DMA
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 7d3c90c..abd93c4 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -126,6 +126,7 @@ void mainboard_romstage_entry(unsigned long bist)
 		.dimm_channel0_disabled = 2,
 		.dimm_channel1_disabled = 2,
 		.max_ddr3_freq = 1600,
+		.usb_xhci_on_resume = 1,
 		.usb2_ports = {
 			/* Length, Enable, OCn#, Location */
 			{ 0x0080, 1, 0,			/* P0: HOST PORT */