[coreboot-gerrit] Patch merged into coreboot/master: 1101a71 spi: add Kconfig variable for dual-output read enable

gerrit at coreboot.org gerrit at coreboot.org
Wed Sep 17 19:56:18 CEST 2014


the following patch was just integrated into master:
commit 1101a71219794b3c070dc67df2f9530b05c4c0fb
Author: David Hendricks <dhendrix at chromium.org>
Date:   Fri Nov 22 18:41:38 2013 -0800

    spi: add Kconfig variable for dual-output read enable
    
    Add a Kconfig variable so that driver code knows whether
    or not to use dual-output reads.
    
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Old-Change-Id: I31d23bfedd91521d719378ec573e33b381ebd2c5
    Reviewed-on: https://chromium-review.googlesource.com/177834
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit de6869a3350041c6823427787971efc9fcf469b8)
    
    tegra124: implement x2 mode for SPI transfers on CBFS media
    
    This implements x2 mode when reading CBFS media over SPI.
    
    In theory this effectively doubles our throughput, though the initial
    results were almost negligibly better. Using a logic analyzer we see
    a pattern of 12 clocks, ~70ns delay, 4 clocks, ~310ns delay. So if we
    want to see further gains here then we'll probably need to tune AHB
    arbitration and utilization to eliminate bubbles/stalls when copying
    from APB DMA.
    
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Old-Change-Id: I33d6ae30923fc42b4dc7103d029085985472cf3e
    Reviewed-on: https://chromium-review.googlesource.com/177835
    Reviewed-by: Tom Warren <twarren at nvidia.com>
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit 29289223362b12e84da5cbb130f285c6b9d314cc)
    
    nyan: turn on dual-output reads for SPI flash
    
    Nyan's SPI chip is capable of dual-output reads, so let's use it.
    
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    
    Old-Change-Id: I51a97c05aa25442d8ddcc4e3e35a2507d91a64df
    Reviewed-on: https://chromium-review.googlesource.com/177836
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Commit-Queue: David Hendricks <dhendrix at chromium.org>
    Tested-by: David Hendricks <dhendrix at chromium.org>
    (cherry picked from commit 62de0889a9cfc5686800645d05e21e272e4beb5c)
    
    Squashed three commits to enable dual output spi reads for nyan.
    Also fixed the spi_xfer interface that has been updated to use bytes
    instead of bits.
    
    Change-Id: I750a177576175b297f61e1b10eac6db15e75aa6e
    Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
    Reviewed-on: http://review.coreboot.org/6909
    Tested-by: build bot (Jenkins)
    Reviewed-by: David Hendricks <dhendrix at chromium.org>


See http://review.coreboot.org/6909 for details.

-gerrit



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