[coreboot-gerrit] Patch set updated for coreboot: 26f245f bd82x6x: Consolidate early native USB init
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Thu Sep 18 21:20:06 CEST 2014
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6923
-gerrit
commit 26f245fed62df6920d33d842b47779436f6eb81e
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Wed Sep 17 02:38:51 2014 +0200
bd82x6x: Consolidate early native USB init
Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/lenovo/t530/romstage.c | 56 +++++------------
src/mainboard/lenovo/x220/romstage.c | 56 +++++------------
src/mainboard/lenovo/x230/romstage.c | 56 +++++------------
src/southbridge/intel/bd82x6x/Makefile.inc | 10 +--
src/southbridge/intel/bd82x6x/early_usb_native.c | 77 ++++++++++++++++++++++++
src/southbridge/intel/bd82x6x/pch.h | 11 ++++
6 files changed, 141 insertions(+), 125 deletions(-)
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index c2f0a4b..89a5cb4 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -110,45 +110,6 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-static void init_usb(void)
-{
- const u32 rcba_dump[64] = {
- /* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57,
- /* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b,
- /* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153,
- /* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000,
- /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
- /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
- /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448,
- /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000,
- /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- };
- int i;
- /* Activate PMBAR. */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
-
- /* Unlock registers. */
- outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
-
- for (i = 0; i < 64; i++)
- write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
-
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
-
- /* Relock registers. */
- outw (0x0000, DEFAULT_PMBASE | 0x003c);
-}
-
-
void main(unsigned long bist)
{
int s3resume = 0;
@@ -184,7 +145,22 @@ void main(unsigned long bist)
outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3);
outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3);
- init_usb();
+ early_usb_init((struct southbridge_usb_port []) {
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 2, 3 },
+ { 1, 1, -1 },
+ { 1, 1, -1 },
+ { 1, 0, -1 },
+ { 0, 0, -1 },
+ { 1, 2, -1 },
+ { 1, 0, -1 },
+ { 1, 1, 5 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 3, -1 },
+ { 1, 1, -1 },
+ });
/* Initialize console device(s) */
console_init();
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index b989ecb..7d97f12 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -108,45 +108,6 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-static void
-init_usb (void)
-{
- const u32 rcba_dump[64] = {
- /* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57,
- /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153,
- /* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57,
- /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
- /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050,
- /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
- /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000,
- /* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000,
- /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- };
- int i;
- /* Activate PMBAR. */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
-
- /* Unlock registers. */
- outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
-
- for (i = 0; i < 64; i++)
- write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
-
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
-
- /* Relock registers. */
- outw (0x0000, DEFAULT_PMBASE | 0x003c);
-}
-
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
@@ -182,7 +143,22 @@ void main(unsigned long bist)
outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44);
outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48);
- init_usb();
+ early_usb_init((struct southbridge_usb_port []) {
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, -1 },
+ { 1, 1, -1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 1, 6 },
+ { 1, 1, 5 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ });
/* Initialize console device(s) */
console_init();
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 16a17c2..c2a0ae7 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -109,45 +109,6 @@ static void rcba_config(void)
RCBA32(BUC) = 0;
}
-static void
-init_usb (void)
-{
- const u32 rcba_dump[64] = {
- /* 3500 */ 0x20000153, 0x20000153, 0x20000f57, 0x20000f57,
- /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x2000055b,
- /* 3520 */ 0x20000153, 0x2000055b, 0x20000f57, 0x20000f57,
- /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
- /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
- /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
- /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000040,
- /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000,
- /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- };
- int i;
- /* Activate PMBAR. */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
-
- /* Unlock registers. */
- outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
-
- for (i = 0; i < 64; i++)
- write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
-
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
-
- /* Relock registers. */
- outw (0x0000, DEFAULT_PMBASE | 0x003c);
-}
-
#include <cpu/intel/romstage.h>
void main(unsigned long bist)
{
@@ -173,7 +134,22 @@ void main(unsigned long bist)
setup_pch_gpios(&x230_gpio_map);
- init_usb();
+ early_usb_init((struct southbridge_usb_port []) {
+ { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
+ { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
+ { 1, 1, 3 }, /* P2: dock, OC 3 */
+ { 1, 1, -1 }, /* P3: wwan, no OC */
+ { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */
+ { 1, 1, -1 }, /* P5: Expresscard, no OC */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 1, 2, -1 }, /* P7: dock, no OC */
+ { 1, 0, -1 },
+ { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */
+ { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
+ { 1, 1, -1 }, /* P11: bluetooth, no OC. */
+ { 1, 1, -1 }, /* P12: wlan, no OC */
+ { 1, 1, -1 }, /* P13: webcam, no OC */
+ });
/* Initialize console device(s) */
console_init();
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index b79b85a..3d33edc 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -47,14 +47,14 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
-romstage-y += early_usb.c early_smbus.c me_status.c gpio.c
+romstage-y += early_smbus.c me_status.c gpio.c
romstage-y += reset.c
romstage-y += early_spi.c early_pch.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
-romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
+romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c
+romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c
+romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
+romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c
new file mode 100644
index 0000000..2afe8d3
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/early_usb_native.c
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */
+#include "pch.h"
+
+void
+early_usb_init (const struct southbridge_usb_port *portmap)
+{
+ u32 reg32;
+ const u32 rcba_dump[8] = {
+ /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
+ /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
+ };
+ const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 };
+ int i;
+ /* Activate PMBAR. */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+
+ /* Unlock registers. */
+ outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
+ for (i = 0; i < 14; i++)
+ write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i),
+ currents[portmap[i].current]);
+ for (i = 0; i < 10; i++)
+ write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0);
+
+ for (i = 0; i < 8; i++)
+ write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]);
+ for (i = 0; i < 8; i++)
+ write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0);
+ reg32 = 0;
+ for (i = 0; i < 14; i++)
+ if (!portmap[i].enabled)
+ reg32 |= (1 << i);
+ write32 (DEFAULT_RCBABASE | 0x359c, reg32);
+ reg32 = 0;
+ for (i = 0; i < 8; i++)
+ if (portmap[i].enabled && portmap[i].oc_pin >= 0)
+ reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
+ write32 (DEFAULT_RCBABASE | 0x35a0, reg32);
+ reg32 = 0;
+ for (i = 8; i < 14; i++)
+ if (portmap[i].enabled && portmap[i].oc_pin >= 4)
+ reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
+ write32 (DEFAULT_RCBABASE | 0x35a4, reg32);
+ for (i = 0; i < 22; i++)
+ write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
+
+ pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
+
+ /* Relock registers. */
+ outw (0x0000, DEFAULT_PMBASE | 0x003c);
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index aabf617..7a796df 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -77,6 +77,17 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
void early_thermal_init(void);
void early_pch_init_native(void);
int southbridge_detect_s3_resume(void);
+
+struct southbridge_usb_port
+{
+ int enabled;
+ int current;
+ int oc_pin;
+};
+
+void
+early_usb_init (const struct southbridge_usb_port *portmap);
+
#endif
#endif
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