[coreboot-gerrit] Patch set updated for coreboot: 1d32c0b cmos: Rename the CMOS related functions.
Isaac Christensen (isaac.christensen@se-eng.com)
gerrit at coreboot.org
Thu Sep 25 23:19:10 CEST 2014
Isaac Christensen (isaac.christensen at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6977
-gerrit
commit 1d32c0b62161ee218b1b5337bb65180a44b68afc
Author: Gabe Black <gabeblack at google.com>
Date: Wed Apr 30 17:12:25 2014 -0700
cmos: Rename the CMOS related functions.
Most of the code related to the mc146818 is not related to the RTC and is
really for managing the CMOS storage. Since we intend to add a generic API
for RTC drivers it's inconvenient for those functions to have an rtc_ prefix.
This CL renames those functions so they start with cmos_ instead. There are
some places where rtc_init was called with a comment that says something about
starting the RTC. That wasn't correct before (the RTC is always running), but
it looks a little odd now that the function is called cmos_init.
This CL also opportunistically cleans up some style problems in this file.
Signed-off-by: Gabe Black <gabeblack at google.com>
Reviewed-on: https://chromium-review.googlesource.com/197794
Reviewed-by: Gabe Black <gabeblack at chromium.org>
Tested-by: Gabe Black <gabeblack at chromium.org>
Commit-Queue: Gabe Black <gabeblack at chromium.org>
(cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788)
Removed the addition of stdint.h to mc146818rtc.h since
types.h is now included. Changed rtc_init to cmos_init for
fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex.
Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c
Signed-off-by: Isaac Christensen <isaac.christensen at se-eng.com>
---
src/drivers/pc80/mc146818rtc.c | 142 ++++++++++++------------
src/include/pc80/mc146818rtc.h | 4 +-
src/northbridge/via/cx700/lpc.c | 2 +-
src/northbridge/via/vx800/lpc.c | 2 +-
src/soc/intel/baytrail/southcluster.c | 2 +-
src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 +-
src/southbridge/amd/agesa/hudson/lpc.c | 8 +-
src/southbridge/amd/amd8111/lpc.c | 2 +-
src/southbridge/amd/cimx/sb700/late.c | 8 +-
src/southbridge/amd/cimx/sb800/late.c | 8 +-
src/southbridge/amd/cimx/sb900/late.c | 8 +-
src/southbridge/amd/cs5536/cs5536.c | 2 +-
src/southbridge/amd/sb600/lpc.c | 2 +-
src/southbridge/amd/sb600/sm.c | 2 +-
src/southbridge/amd/sb700/lpc.c | 2 +-
src/southbridge/amd/sb700/sm.c | 2 +-
src/southbridge/amd/sb800/lpc.c | 2 +-
src/southbridge/amd/sb800/sm.c | 2 +-
src/southbridge/broadcom/bcm5785/lpc.c | 2 +-
src/southbridge/dmp/vortex86ex/southbridge.c | 2 +-
src/southbridge/intel/bd82x6x/lpc.c | 2 +-
src/southbridge/intel/esb6300/lpc.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +-
src/southbridge/intel/fsp_rangeley/early_init.c | 2 +-
src/southbridge/intel/i3100/lpc.c | 2 +-
src/southbridge/intel/i82371eb/isa.c | 2 +-
src/southbridge/intel/i82801ax/lpc.c | 2 +-
src/southbridge/intel/i82801bx/lpc.c | 2 +-
src/southbridge/intel/i82801cx/lpc.c | 2 +-
src/southbridge/intel/i82801dx/lpc.c | 2 +-
src/southbridge/intel/i82801ex/lpc.c | 2 +-
src/southbridge/intel/i82801gx/lpc.c | 2 +-
src/southbridge/intel/i82801ix/lpc.c | 2 +-
src/southbridge/intel/ibexpeak/lpc.c | 2 +-
src/southbridge/intel/lynxpoint/lpc.c | 2 +-
src/southbridge/nvidia/ck804/lpc.c | 2 +-
src/southbridge/nvidia/mcp55/lpc.c | 2 +-
src/southbridge/sis/sis966/lpc.c | 2 +-
src/southbridge/via/vt8231/lpc.c | 2 +-
src/southbridge/via/vt8235/lpc.c | 2 +-
src/southbridge/via/vt8237r/lpc.c | 2 +-
41 files changed, 125 insertions(+), 123 deletions(-)
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index c54f6ce..9670e9c 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -10,7 +10,8 @@
#endif
#include <arch/acpi.h>
-static void rtc_update_cmos_date(u8 has_century)
+
+static void cmos_update_date(u8 has_century)
{
/* Now setup a default date equals to the build date */
cmos_write(0, RTC_CLK_SECOND);
@@ -24,28 +25,27 @@ static void rtc_update_cmos_date(u8 has_century)
}
#if CONFIG_USE_OPTION_TABLE
-static int rtc_checksum_valid(int range_start, int range_end, int cks_loc)
+static int cmos_checksum_valid(int range_start, int range_end, int cks_loc)
{
int i;
u16 sum, old_sum;
sum = 0;
- for(i = range_start; i <= range_end; i++) {
+ for (i = range_start; i <= range_end; i++)
sum += cmos_read(i);
- }
- old_sum = ((cmos_read(cks_loc)<<8) | cmos_read(cks_loc+1))&0x0ffff;
+ old_sum = ((cmos_read(cks_loc) << 8) | cmos_read(cks_loc + 1)) &
+ 0x0ffff;
return sum == old_sum;
}
-static void rtc_set_checksum(int range_start, int range_end, int cks_loc)
+static void cmos_set_checksum(int range_start, int range_end, int cks_loc)
{
int i;
u16 sum;
sum = 0;
- for(i = range_start; i <= range_end; i++) {
+ for (i = range_start; i <= range_end; i++)
sum += cmos_read(i);
- }
cmos_write(((sum >> 8) & 0x0ff), cks_loc);
- cmos_write(((sum >> 0) & 0x0ff), cks_loc+1);
+ cmos_write(((sum >> 0) & 0x0ff), cks_loc + 1);
}
#endif
@@ -60,7 +60,7 @@ static void rtc_set_checksum(int range_start, int range_end, int cks_loc)
#endif
#ifndef __SMM__
-void rtc_init(int invalid)
+void cmos_init(int invalid)
{
int cmos_invalid = 0;
int checksum_invalid = 0;
@@ -87,7 +87,7 @@ void rtc_init(int invalid)
cmos_invalid = !(x & RTC_VRT);
/* See if there is a CMOS checksum error */
- checksum_invalid = !rtc_checksum_valid(PC_CKS_RANGE_START,
+ checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START,
PC_CKS_RANGE_END,PC_CKS_LOC);
#define CLEAR_CMOS 0
@@ -102,13 +102,11 @@ void rtc_init(int invalid)
cmos_write(0, 0x01);
cmos_write(0, 0x03);
cmos_write(0, 0x05);
- for(i = 10; i < 128; i++) {
+ for (i = 10; i < 128; i++)
cmos_write(0, i);
- }
#endif
- if (cmos_invalid) {
- rtc_update_cmos_date(RTC_HAS_NO_ALTCENTURY);
- }
+ if (cmos_invalid)
+ cmos_update_date(RTC_HAS_NO_ALTCENTURY);
printk(BIOS_WARNING, "RTC:%s%s%s%s\n",
invalid?" Clear requested":"",
@@ -126,30 +124,29 @@ void rtc_init(int invalid)
#if CONFIG_USE_OPTION_TABLE
/* See if there is a LB CMOS checksum error */
- checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
+ checksum_invalid = !cmos_checksum_valid(LB_CKS_RANGE_START,
LB_CKS_RANGE_END,LB_CKS_LOC);
- if(checksum_invalid)
+ if (checksum_invalid)
printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n");
/* Make certain we have a valid checksum */
- rtc_set_checksum(PC_CKS_RANGE_START,
- PC_CKS_RANGE_END,PC_CKS_LOC);
+ cmos_set_checksum(PC_CKS_RANGE_START, PC_CKS_RANGE_END, PC_CKS_LOC);
#endif
/* Clear any pending interrupts */
- (void) cmos_read(RTC_INTR_FLAGS);
+ cmos_read(RTC_INTR_FLAGS);
}
#endif
#if CONFIG_USE_OPTION_TABLE
-/* This routine returns the value of the requested bits
- input bit = bit count from the beginning of the cmos image
- length = number of bits to include in the value
- ret = a character pointer to where the value is to be returned
- output the value placed in ret
- returns CB_SUCCESS = successful, cb_err code if an error occurred
-*/
+/*
+ * This routine returns the value of the requested bits.
+ * input bit = bit count from the beginning of the cmos image
+ * length = number of bits to include in the value
+ * ret = a character pointer to where the value is to be returned
+ * returns CB_SUCCESS = successful, cb_err code if an error occurred
+ */
static enum cb_err get_cmos_value(unsigned long bit, unsigned long length,
void *vret)
{
@@ -158,21 +155,22 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length,
unsigned long i;
unsigned char uchar;
- /* The table is checked when it is built to ensure all
- values are valid. */
+ /*
+ * The table is checked when it is built to ensure all
+ * values are valid.
+ */
ret = vret;
- byte=bit/8; /* find the byte where the data starts */
- byte_bit=bit%8; /* find the bit in the byte where the data starts */
- if(length<9) { /* one byte or less */
+ byte = bit / 8; /* find the byte where the data starts */
+ byte_bit = bit % 8; /* find the bit in the byte where the data starts */
+ if (length < 9) { /* one byte or less */
uchar = cmos_read(byte); /* load the byte */
uchar >>= byte_bit; /* shift the bits to byte align */
/* clear unspecified bits */
- ret[0] = uchar & ((1 << length) -1);
- }
- else { /* more that one byte so transfer the whole bytes */
- for(i=0;length;i++,length-=8,byte++) {
+ ret[0] = uchar & ((1 << length) - 1);
+ } else { /* more that one byte so transfer the whole bytes */
+ for (i = 0; length; i++, length -= 8, byte++) {
/* load the byte */
- ret[i]=cmos_read(byte);
+ ret[i] = cmos_read(byte);
}
}
return CB_SUCCESS;
@@ -183,7 +181,7 @@ enum cb_err get_option(void *dest, const char *name)
struct cmos_option_table *ct;
struct cmos_entries *ce;
size_t namelen;
- int found=0;
+ int found = 0;
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
@@ -196,22 +194,22 @@ enum cb_err get_option(void *dest, const char *name)
"Options are disabled\n");
return CB_CMOS_LAYOUT_NOT_FOUND;
}
- ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
- for(;ce->tag==LB_TAG_OPTION;
- ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(; ce->tag == LB_TAG_OPTION;
+ ce = (struct cmos_entries*)((unsigned char *)ce + ce->size)) {
if (memcmp(ce->name, name, namelen) == 0) {
- found=1;
+ found = 1;
break;
}
}
- if(!found) {
+ if (!found) {
printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
return CB_CMOS_OPTION_NOT_FOUND;
}
- if(get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS)
+ if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;
- if(!rtc_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END,LB_CKS_LOC))
+ if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC))
return CB_CMOS_CHECKSUM_INVALID;
return CB_SUCCESS;
}
@@ -226,9 +224,9 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
unsigned int chksum_update_needed = 0;
ret = vret;
- byte = bit / 8; /* find the byte where the data starts */
- byte_bit = bit % 8; /* find the bit in the byte where the data starts */
- if(length <= 8) { /* one byte or less */
+ byte = bit / 8; /* find the byte where the data starts */
+ byte_bit = bit % 8; /* find the bit where the data starts */
+ if (length <= 8) { /* one byte or less */
mask = (1 << length) - 1;
mask <<= byte_bit;
@@ -238,19 +236,20 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
cmos_write(uchar, byte);
if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END)
chksum_update_needed = 1;
- } else { /* more that one byte so transfer the whole bytes */
+ } else { /* more that one byte so transfer the whole bytes */
if (byte_bit || length % 8)
return CB_ERR_ARG;
- for(i=0; length; i++, length-=8, byte++)
+ for (i = 0; length; i++, length -= 8, byte++)
cmos_write(ret[i], byte);
- if (byte >= LB_CKS_RANGE_START && byte <= LB_CKS_RANGE_END)
+ if (byte >= LB_CKS_RANGE_START &&
+ byte <= LB_CKS_RANGE_END)
chksum_update_needed = 1;
}
if (chksum_update_needed) {
- rtc_set_checksum(LB_CKS_RANGE_START,
- LB_CKS_RANGE_END,LB_CKS_LOC);
+ cmos_set_checksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END,
+ LB_CKS_LOC);
}
return CB_SUCCESS;
}
@@ -262,7 +261,7 @@ enum cb_err set_option(const char *name, void *value)
struct cmos_entries *ce;
unsigned long length;
size_t namelen;
- int found=0;
+ int found = 0;
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
@@ -271,18 +270,19 @@ enum cb_err set_option(const char *name, void *value)
ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT, NULL);
if (!ct) {
- printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n");
+ printk(BIOS_ERR, "cmos_layout.bin could not be found. "
+ "Options are disabled\n");
return CB_CMOS_LAYOUT_NOT_FOUND;
}
- ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
- for(;ce->tag==LB_TAG_OPTION;
- ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+ ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+ for(; ce->tag == LB_TAG_OPTION;
+ ce = (struct cmos_entries*)((unsigned char *)ce + ce->size)) {
if (memcmp(ce->name, name, namelen) == 0) {
- found=1;
+ found = 1;
break;
}
}
- if(!found) {
+ if (!found) {
printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
return CB_CMOS_OPTION_NOT_FOUND;
}
@@ -308,17 +308,19 @@ enum cb_err set_option(const char *name, void *value)
* hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need
* to make sure the date is valid.
*/
-void rtc_check_update_cmos_date(u8 has_century)
+void cmos_check_update_date(u8 has_century)
{
u8 year, century;
- /* Note: We need to check if the hardware supports RTC_CLK_ALTCENTURY. */
- century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0;
- year = cmos_read(RTC_CLK_YEAR);
+ /* Note: Need to check if the hardware supports RTC_CLK_ALTCENTURY. */
+ century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0;
+ year = cmos_read(RTC_CLK_YEAR);
- /* TODO: If century is 0xFF, 100% that the cmos is cleared.
- * Other than that, so far rtc_year is the only entry to check if the date is valid. */
- if (century > 0x99 || year > 0x99) { /* Invalid date */
- rtc_update_cmos_date(has_century);
- }
+ /*
+ * TODO: If century is 0xFF, 100% that the cmos is cleared.
+ * Other than that, so far rtc_year is the only entry to check
+ * if the date is valid.
+ */
+ if (century > 0x99 || year > 0x99) /* Invalid date */
+ cmos_update_date(has_century);
}
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index a401821..3d65909 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -172,8 +172,8 @@ static inline void cmos_write32(u8 offset, u32 value)
#endif
#if !defined(__ROMCC__)
-void rtc_init(int invalid);
-void rtc_check_update_cmos_date(u8 has_century);
+void cmos_init(int invalid);
+void cmos_check_update_date(u8 has_century);
#if CONFIG_USE_OPTION_TABLE
enum cb_err set_option(const char *name, void *val);
enum cb_err get_option(void *dest, const char *name);
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index c09fbb4..da3e2ce 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -283,7 +283,7 @@ static void cx700_lpc_init(struct device *dev)
setup_i8259();
/* Start the Real Time Clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index 1908a8a..c2a8a1d 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -295,7 +295,7 @@ static void vx800_sb_init(struct device *dev)
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 49e4c91..4be5458 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -141,7 +141,7 @@ static void sc_rtc_init(void)
printk(BIOS_DEBUG, "RTC failure.\n");
}
- rtc_init(rtc_fail);
+ cmos_init(rtc_fail);
}
static void sc_init(device_t dev)
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index a63156f..2d41ed3 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -105,7 +105,7 @@ static void baytrail_rtc_init(void)
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
}
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* Entry from cache-as-ram.inc. */
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 20212ef..1f60bc4 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -70,14 +70,14 @@ static void lpc_init(device_t dev)
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
}
static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index e9bd5fc..da9b4f8 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -71,7 +71,7 @@ static void lpc_init(struct device *dev)
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 42330ca..20da073 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -80,14 +80,14 @@ static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b132bf1..7d6e221 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -132,14 +132,14 @@ static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 7303bdc..8d9b486 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -102,14 +102,14 @@ static void lpc_init(device_t dev)
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index e305594..1f7eab8 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -245,7 +245,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
msr.lo = RTC_MONA;
wrmsr(MDD_RTC_MONA_IND, msr);
- rtc_init(0);
+ cmos_init(0);
isa_dma_init();
}
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 7ef49d1..517ab59 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -59,7 +59,7 @@ static void lpc_init(device_t dev)
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb600_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 8de39a6..a8e72c2 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -169,7 +169,7 @@ static void sm_init(device_t dev)
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index a175210..0cbf854 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -81,7 +81,7 @@ static void lpc_init(device_t dev)
}
#endif
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
void backup_top_of_ram(uint64_t ramtop)
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 0fb6556..8bb5378 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -197,7 +197,7 @@ static void sm_init(device_t dev)
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 12fd96f..7a4dd83 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -67,7 +67,7 @@ static void lpc_init(device_t dev)
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb800_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 315bc20..acdfb09 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -111,7 +111,7 @@ static void sm_init(device_t dev)
pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
byte = pm_ioread(0x8);
byte |= 1 << 2 | 1 << 4;
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index 834f0a1..af79892 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -33,7 +33,7 @@
static void lpc_init(device_t dev)
{
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index a2b1246..d4f263b 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -595,7 +595,7 @@ static void southbridge_init(struct device *dev)
pci_routing_fixup(dev);
fix_cmos_rtc_time();
- rtc_init(0);
+ cmos_init(0);
/* Check keyboard controller ready. If timeout, reload firmware code
* and try again.
*/
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index fa05d54..cd2bd6f 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -293,7 +293,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c
index 67bcadc..b5b77ef 100644
--- a/src/southbridge/intel/esb6300/lpc.c
+++ b/src/southbridge/intel/esb6300/lpc.c
@@ -297,7 +297,7 @@ static void lpc_init(struct device *dev)
esb6300_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 8c15967..66e0b1f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -300,7 +300,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* CougarPoint PCH Power Management init */
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 0697785..bd3d12c 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -69,7 +69,7 @@ static void reset_rtc(void)
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
}
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
void rangeley_sb_early_initialization(void)
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index abd0653..f0ce6a6 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -374,7 +374,7 @@ static void lpc_init(struct device *dev)
i3100_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 5605106..5261fba 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -64,7 +64,7 @@ static void isa_init(struct device *dev)
u32 reg32;
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/*
* Enable special cycles, needed for soft poweroff.
diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c
index 212c95f..11519c1 100644
--- a/src/southbridge/intel/i82801ax/lpc.c
+++ b/src/southbridge/intel/i82801ax/lpc.c
@@ -190,7 +190,7 @@ static void i82801ax_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STA);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c
index 13b1599..278d65c 100644
--- a/src/southbridge/intel/i82801bx/lpc.c
+++ b/src/southbridge/intel/i82801bx/lpc.c
@@ -205,7 +205,7 @@ static void i82801bx_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c
index f9c0ece..f6c33b7 100644
--- a/src/southbridge/intel/i82801cx/lpc.c
+++ b/src/southbridge/intel/i82801cx/lpc.c
@@ -108,7 +108,7 @@ static void i82801cx_rtc_init(struct device *dev)
dword = pci_read_config32(dev, GEN_STS);
rtc_failed |= dword & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index de09b16..1b23fad 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -200,7 +200,7 @@ static void i82801dx_rtc_init(struct device *dev)
}
reg32 = pci_read_config32(dev, GEN_STS);
rtc_failed |= reg32 & (1 << 2);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
/* Enable access to the upper 128 byte bank of CMOS RAM. */
pci_write_config8(dev, RTC_CONF, 0x04);
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index fb1586e..1823e65 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -308,7 +308,7 @@ static void lpc_init(struct device *dev)
i82801ex_gpio_init(dev);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index b208339..b39aeab 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -290,7 +290,7 @@ static void i82801gx_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index ea88111..9a91253 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -322,7 +322,7 @@ static void i82801ix_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void enable_hpet(void)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 7580aa9..28c084e 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -293,7 +293,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
static void mobile5_pm_init(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index d1a7203..9c4c483 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -301,7 +301,7 @@ static void pch_rtc_init(struct device *dev)
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
- rtc_init(rtc_failed);
+ cmos_init(rtc_failed);
}
/* LynxPoint PCH Power Management init */
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index b3a9b00..d4c4f20 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -161,7 +161,7 @@ static void lpc_init(device_t dev)
outb(byte, 0x70);
/* Initialize the real time clock (RTC). */
- rtc_init(0);
+ cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 585232d..e56c4a9 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -146,7 +146,7 @@ static void lpc_init(device_t dev)
outb(byte, 0x70);
/* Initialize the real time clock. */
- rtc_init(0);
+ cmos_init(0);
/* Initialize ISA DMA. */
isa_dma_init();
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 824bb6a..0e11c6f 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -148,7 +148,7 @@ static void lpc_init(device_t dev)
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c
index 40854db..c6b74fd 100644
--- a/src/southbridge/via/vt8231/lpc.c
+++ b/src/southbridge/via/vt8231/lpc.c
@@ -121,7 +121,7 @@ static void vt8231_init(struct device *dev)
//ethernet_fixup();
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
static void vt8231_read_resources(device_t dev)
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c
index b355ad0..2c78481 100644
--- a/src/southbridge/via/vt8235/lpc.c
+++ b/src/southbridge/via/vt8235/lpc.c
@@ -209,7 +209,7 @@ static void vt8235_init(struct device *dev)
pci_write_config8(dev, 0x40, 0x54);
// Start the rtc
- rtc_init(0);
+ cmos_init(0);
}
/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 5ddd816..9e8f6f6 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -565,7 +565,7 @@ static void vt8237_common_init(struct device *dev)
setup_pm(dev);
/* Start the RTC. */
- rtc_init(0);
+ cmos_init(0);
}
static void vt8237r_read_resources(device_t dev)
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