[coreboot-gerrit] Patch merged into coreboot/master: 8ef55ee Broadwell: Revise programming flow for write-once registers
gerrit at coreboot.org
gerrit at coreboot.org
Thu Apr 2 17:27:56 CEST 2015
the following patch was just integrated into master:
commit 8ef55ee9969de3003eae9e3113b7497799ba14ec
Author: Kenji Chen <kenji.chen at intel.com>
Date: Thu Sep 25 21:34:42 2014 +0800
Broadwell: Revise programming flow for write-once registers
Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.
Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9
Original-BUG=chrome-os-partner:31424.
Original-TEST=Build a image and check the programming value is correct on
Original-Samus.
Original-Signed-off-by: Kenji Chen <kenji.chen at intel.com>
Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Original-Reviewed-on: https://chromium-review.googlesource.com/219985
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844
Reviewed-on: http://review.coreboot.org/9209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi at google.com>
See http://review.coreboot.org/9209 for details.
-gerrit
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