[coreboot-gerrit] Patch set updated for coreboot: 0b738d2 t132: Enable SMMU translations
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Fri Apr 3 14:48:10 CEST 2015
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9258
-gerrit
commit 0b738d2249969f7233b25ba05c0c5e47b1a87c90
Author: Furquan Shaikh <furquan at google.com>
Date: Fri Oct 10 01:31:02 2014 -0700
t132: Enable SMMU translations
BUG=None
BRANCH=None
TEST=Verified by reading back the value of SMMU_CONFIG register that enable bit
is set to 1
Original-Change-Id: Iccc870141f9b9729971bf12119f9f3dae8181a43
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/222770
Original-Reviewed-by: Olof Johansson <olofj at chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
(cherry picked from commit a06b36f9003d801709d83a8faed6fc04bb91df1b)
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Change-Id: Iae3949940a5a0efa2761542974d5c209178ce397
---
src/soc/nvidia/tegra132/addressmap.c | 3 +++
src/soc/nvidia/tegra132/mc.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/src/soc/nvidia/tegra132/addressmap.c b/src/soc/nvidia/tegra132/addressmap.c
index 3df15b7..a18e1b8 100644
--- a/src/soc/nvidia/tegra132/addressmap.c
+++ b/src/soc/nvidia/tegra132/addressmap.c
@@ -188,4 +188,7 @@ void trustzone_region_init(void)
/* Set the carveout region. */
write32(tz_base_mib << 20, &mc->security_cfg0);
write32(tz_size_mib, &mc->security_cfg1);
+
+ /* Enable SMMU translations */
+ write32(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
}
diff --git a/src/soc/nvidia/tegra132/mc.h b/src/soc/nvidia/tegra132/mc.h
index c9faa49..3ce7900 100644
--- a/src/soc/nvidia/tegra132/mc.h
+++ b/src/soc/nvidia/tegra132/mc.h
@@ -117,6 +117,8 @@ struct tegra_mc_regs {
};
enum {
+ MC_SMMU_CONFIG_ENABLE = 1,
+
MC_EMEM_CFG_SIZE_MB_SHIFT = 0,
MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff,
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