[coreboot-gerrit] New patch to review for coreboot: 32a7a81 pistachio: modify memory layout
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 7 13:01:30 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9337
-gerrit
commit 32a7a81c7e7a5ae51cdebf5fc02c51bc23b3f375
Author: Vadim Bendebury <vbendeb at chromium.org>
Date: Tue Nov 11 20:14:47 2014 -0800
pistachio: modify memory layout
With the code now running on the FPGA board it makes sense to correct
the memory layout definitions to match the actual hardware.
Note that the latest FPGA board firmware introduced support of the
additional 128KB of SRAM (called GRAM) at base address of 0x9a000000.
These are still interim values, which will be tweaked when the actual
bring up board is available.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=the code put into SPI NOR flash boots all the way to ramstage.
Change-Id: I00aa5bc3aabba50df2187bb208cf2fcd11b26b3d
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: a6378be5cd304744b40c57a34d7a276233d45779
Original-Change-Id: I50183c2d5f9017801d5c8a7a7addf08efa492b35
Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229203
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 21c3d73..554ebfc 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -21,18 +21,19 @@
#include <arch/header.ld>
-/* TODO: This should be revised by someone who understands the SoC better. */
-
SECTIONS
{
- CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */
-
DRAM_START(0x80000000)
RAMSTAGE(0x80000000, 128K)
- /* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */
- BOOTBLOCK(0x9B000000, 16K)
- ROMSTAGE(0x9B004000, 40K)
- STACK(0x9B00E000, 6K)
- PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K)
+ /* GRAM becomes the SRAM. */
+ SRAM_START(0x9a000000)
+ BOOTBLOCK(0x9a000000, 16K)
+ ROMSTAGE(0x9a004000, 32K)
+ STACK(0x9a01c000, 8K)
+ PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
+ SRAM_END(0x9a020000)
+
+ /* Let's use SRAM for CBFS cache. */
+ CBFS_CACHE(0x9b000000, 64K)
}
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