[coreboot-gerrit] New patch to review for coreboot: 9657f08 broadwell: Change all SoC headers to <soc/headername.h> system
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 7 17:53:32 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9364
-gerrit
commit 9657f0831c635c82d9123153bc19b79018f26ef4
Author: Julius Werner <jwerner at chromium.org>
Date: Mon Oct 20 13:46:39 2014 -0700
broadwell: Change all SoC headers to <soc/headername.h> system
This patch aligns broadwell to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.
Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/samus/acpi_tables.c | 4 +-
src/mainboard/google/samus/chromeos.c | 2 +-
src/mainboard/google/samus/fadt.c | 2 +-
src/mainboard/google/samus/gpio.h | 2 +-
src/mainboard/google/samus/pei_data.c | 6 +-
src/mainboard/google/samus/romstage.c | 12 +-
src/mainboard/google/samus/smihandler.c | 14 +-
src/mainboard/google/samus/spd/spd.c | 6 +-
src/mainboard/intel/wtm2/acpi_tables.c | 4 +-
src/mainboard/intel/wtm2/chromeos.c | 2 +-
src/mainboard/intel/wtm2/fadt.c | 2 +-
src/mainboard/intel/wtm2/gpio.h | 2 +-
src/mainboard/intel/wtm2/mainboard_smi.c | 4 +-
src/mainboard/intel/wtm2/pei_data.c | 6 +-
src/mainboard/intel/wtm2/romstage.c | 8 +-
src/soc/intel/broadwell/Makefile.inc | 2 +-
src/soc/intel/broadwell/acpi.c | 16 +-
src/soc/intel/broadwell/acpi/pch.asl | 2 +-
src/soc/intel/broadwell/acpi/systemagent.asl | 2 +-
src/soc/intel/broadwell/adsp.c | 16 +-
src/soc/intel/broadwell/bootblock/cpu.c | 4 +-
src/soc/intel/broadwell/bootblock/pch.c | 10 +-
src/soc/intel/broadwell/bootblock/systemagent.c | 4 +-
src/soc/intel/broadwell/broadwell/acpi.h | 37 --
src/soc/intel/broadwell/broadwell/adsp.h | 56 ---
src/soc/intel/broadwell/broadwell/cpu.h | 73 ---
src/soc/intel/broadwell/broadwell/device_nvs.h | 44 --
src/soc/intel/broadwell/broadwell/ehci.h | 32 --
src/soc/intel/broadwell/broadwell/gpio.h | 192 --------
src/soc/intel/broadwell/broadwell/iobp.h | 28 --
src/soc/intel/broadwell/broadwell/iomap.h | 62 ---
src/soc/intel/broadwell/broadwell/lpc.h | 93 ----
src/soc/intel/broadwell/broadwell/me.h | 508 ---------------------
src/soc/intel/broadwell/broadwell/msr.h | 109 -----
src/soc/intel/broadwell/broadwell/nvs.h | 71 ---
src/soc/intel/broadwell/broadwell/pch.h | 52 ---
src/soc/intel/broadwell/broadwell/pci_devs.h | 119 -----
src/soc/intel/broadwell/broadwell/pei_data.h | 199 --------
src/soc/intel/broadwell/broadwell/pei_wrapper.h | 49 --
src/soc/intel/broadwell/broadwell/pm.h | 170 -------
src/soc/intel/broadwell/broadwell/ramstage.h | 38 --
src/soc/intel/broadwell/broadwell/rcba.h | 178 --------
src/soc/intel/broadwell/broadwell/reset.h | 25 -
src/soc/intel/broadwell/broadwell/romstage.h | 60 ---
src/soc/intel/broadwell/broadwell/sata.h | 85 ----
src/soc/intel/broadwell/broadwell/serialio.h | 94 ----
src/soc/intel/broadwell/broadwell/smbus.h | 52 ---
src/soc/intel/broadwell/broadwell/smm.h | 73 ---
src/soc/intel/broadwell/broadwell/spi.h | 100 ----
src/soc/intel/broadwell/broadwell/systemagent.h | 133 ------
src/soc/intel/broadwell/broadwell/xhci.h | 61 ---
src/soc/intel/broadwell/chip.c | 6 +-
src/soc/intel/broadwell/cpu.c | 16 +-
src/soc/intel/broadwell/cpu_info.c | 6 +-
src/soc/intel/broadwell/ehci.c | 4 +-
src/soc/intel/broadwell/elog.c | 4 +-
src/soc/intel/broadwell/finalize.c | 12 +-
src/soc/intel/broadwell/gpio.c | 6 +-
src/soc/intel/broadwell/hda.c | 6 +-
src/soc/intel/broadwell/igd.c | 8 +-
src/soc/intel/broadwell/include/soc/acpi.h | 37 ++
src/soc/intel/broadwell/include/soc/adsp.h | 56 +++
src/soc/intel/broadwell/include/soc/cpu.h | 73 +++
src/soc/intel/broadwell/include/soc/device_nvs.h | 44 ++
src/soc/intel/broadwell/include/soc/ehci.h | 32 ++
src/soc/intel/broadwell/include/soc/gpio.h | 192 ++++++++
src/soc/intel/broadwell/include/soc/iobp.h | 28 ++
src/soc/intel/broadwell/include/soc/iomap.h | 62 +++
src/soc/intel/broadwell/include/soc/lpc.h | 93 ++++
src/soc/intel/broadwell/include/soc/me.h | 508 +++++++++++++++++++++
src/soc/intel/broadwell/include/soc/msr.h | 109 +++++
src/soc/intel/broadwell/include/soc/nvs.h | 71 +++
src/soc/intel/broadwell/include/soc/pch.h | 52 +++
src/soc/intel/broadwell/include/soc/pci_devs.h | 119 +++++
src/soc/intel/broadwell/include/soc/pei_data.h | 199 ++++++++
src/soc/intel/broadwell/include/soc/pei_wrapper.h | 49 ++
src/soc/intel/broadwell/include/soc/pm.h | 170 +++++++
src/soc/intel/broadwell/include/soc/ramstage.h | 38 ++
src/soc/intel/broadwell/include/soc/rcba.h | 178 ++++++++
src/soc/intel/broadwell/include/soc/reset.h | 25 +
src/soc/intel/broadwell/include/soc/romstage.h | 60 +++
src/soc/intel/broadwell/include/soc/sata.h | 85 ++++
src/soc/intel/broadwell/include/soc/serialio.h | 94 ++++
src/soc/intel/broadwell/include/soc/smbus.h | 52 +++
src/soc/intel/broadwell/include/soc/smm.h | 73 +++
src/soc/intel/broadwell/include/soc/spi.h | 100 ++++
src/soc/intel/broadwell/include/soc/systemagent.h | 133 ++++++
src/soc/intel/broadwell/include/soc/xhci.h | 61 +++
src/soc/intel/broadwell/iobp.c | 4 +-
src/soc/intel/broadwell/lpc.c | 22 +-
src/soc/intel/broadwell/me.c | 14 +-
src/soc/intel/broadwell/me_status.c | 4 +-
src/soc/intel/broadwell/memmap.c | 4 +-
src/soc/intel/broadwell/minihd.c | 2 +-
src/soc/intel/broadwell/monotonic_timer.c | 2 +-
src/soc/intel/broadwell/pch.c | 14 +-
src/soc/intel/broadwell/pcie.c | 16 +-
src/soc/intel/broadwell/pei_data.c | 8 +-
src/soc/intel/broadwell/pmutil.c | 10 +-
src/soc/intel/broadwell/ramstage.c | 8 +-
src/soc/intel/broadwell/refcode.c | 6 +-
src/soc/intel/broadwell/reset.c | 2 +-
src/soc/intel/broadwell/romstage/cpu.c | 6 +-
src/soc/intel/broadwell/romstage/pch.c | 18 +-
src/soc/intel/broadwell/romstage/power_state.c | 10 +-
src/soc/intel/broadwell/romstage/raminit.c | 16 +-
src/soc/intel/broadwell/romstage/report_platform.c | 10 +-
src/soc/intel/broadwell/romstage/romstage.c | 12 +-
src/soc/intel/broadwell/romstage/smbus.c | 8 +-
src/soc/intel/broadwell/romstage/spi.c | 6 +-
src/soc/intel/broadwell/romstage/stack.c | 2 +-
src/soc/intel/broadwell/romstage/systemagent.c | 8 +-
src/soc/intel/broadwell/romstage/uart.c | 4 +-
src/soc/intel/broadwell/sata.c | 10 +-
src/soc/intel/broadwell/serialio.c | 16 +-
src/soc/intel/broadwell/smbus.c | 6 +-
src/soc/intel/broadwell/smbus_common.c | 4 +-
src/soc/intel/broadwell/smi.c | 8 +-
src/soc/intel/broadwell/smihandler.c | 14 +-
src/soc/intel/broadwell/smmrelocate.c | 10 +-
src/soc/intel/broadwell/spi.c | 2 +-
src/soc/intel/broadwell/stage_cache.c | 2 +-
src/soc/intel/broadwell/systemagent.c | 10 +-
src/soc/intel/broadwell/tsc_freq.c | 4 +-
src/soc/intel/broadwell/usbdebug.c | 2 +-
src/soc/intel/broadwell/xhci.c | 6 +-
126 files changed, 3048 insertions(+), 3048 deletions(-)
diff --git a/src/mainboard/google/samus/acpi_tables.c b/src/mainboard/google/samus/acpi_tables.c
index 738bb3b..a605828 100644
--- a/src/mainboard/google/samus/acpi_tables.c
+++ b/src/mainboard/google/samus/acpi_tables.c
@@ -29,8 +29,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
#include "thermal.h"
void acpi_create_gnvs(global_nvs_t *gnvs)
diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c
index 8e6e572..fc7acff 100644
--- a/src/mainboard/google/samus/chromeos.c
+++ b/src/mainboard/google/samus/chromeos.c
@@ -26,7 +26,7 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
/* SPI Write protect is GPIO 16 */
diff --git a/src/mainboard/google/samus/fadt.c b/src/mainboard/google/samus/fadt.c
index bcc08fd..d68a1ce 100644
--- a/src/mainboard/google/samus/fadt.c
+++ b/src/mainboard/google/samus/fadt.c
@@ -19,7 +19,7 @@
*/
#include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h
index 99bdee6..051532a 100644
--- a/src/mainboard/google/samus/gpio.h
+++ b/src/mainboard/google/samus/gpio.h
@@ -20,7 +20,7 @@
#ifndef SAMUS_GPIO_H
#define SAMUS_GPIO_H
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
#define SAMUS_GPIO_PP3300_AUTOBAHN_EN 23
#define SAMUS_GPIO_SSD_RESET_L 47
diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c
index 05a3ded..6f98a4b 100644
--- a/src/mainboard/google/samus/pei_data.c
+++ b/src/mainboard/google/samus/pei_data.c
@@ -19,9 +19,9 @@
#include <stdint.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c
index 39a23f0..55658f5 100644
--- a/src/mainboard/google/samus/romstage.c
+++ b/src/mainboard/google/samus/romstage.c
@@ -22,12 +22,12 @@
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
-#include <broadwell/cpu.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/pm.h>
-#include <broadwell/romstage.h>
+#include <soc/cpu.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
#include <mainboard/google/samus/spd/spd.h>
#include <mainboard/google/samus/gpio.h>
diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c
index a97f426..faccbc1 100644
--- a/src/mainboard/google/samus/smihandler.c
+++ b/src/mainboard/google/samus/smihandler.c
@@ -21,15 +21,15 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
#include <elog.h>
#include <ec/google/chromeec/ec.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iomap.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
#include "ec.h"
#include "gpio.h"
diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c
index 0051fee..4f4f9ef 100644
--- a/src/mainboard/google/samus/spd/spd.c
+++ b/src/mainboard/google/samus/spd/spd.c
@@ -21,9 +21,9 @@
#include <cbfs.h>
#include <console/console.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/samus/ec.h>
#include <mainboard/google/samus/gpio.h>
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c
index b6c0f9a..2df32a9 100644
--- a/src/mainboard/intel/wtm2/acpi_tables.c
+++ b/src/mainboard/intel/wtm2/acpi_tables.c
@@ -29,8 +29,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
#include "thermal.h"
void acpi_create_gnvs(global_nvs_t *gnvs)
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index fe469f7..b240b84 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -22,7 +22,7 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
/* Compile-time settings for developer and recovery mode. */
#define DEV_MODE_SETTING 1
diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c
index a8811d2..a876e1f 100644
--- a/src/mainboard/intel/wtm2/fadt.c
+++ b/src/mainboard/intel/wtm2/fadt.c
@@ -18,7 +18,7 @@
*/
#include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h
index 47272b8..f4825ba 100644
--- a/src/mainboard/intel/wtm2/gpio.h
+++ b/src/mainboard/intel/wtm2/gpio.h
@@ -20,7 +20,7 @@
#ifndef INTEL_WTM2_GPIO_H
#define INTEL_WTM2_GPIO_H
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */
diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c
index bec0b61..1c4edef 100644
--- a/src/mainboard/intel/wtm2/mainboard_smi.c
+++ b/src/mainboard/intel/wtm2/mainboard_smi.c
@@ -20,8 +20,8 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
-#include <broadwell/nvs.h>
-#include <broadwell/smm.h>
+#include <soc/nvs.h>
+#include <soc/smm.h>
int mainboard_io_trap_handler(int smif)
{
diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c
index e67d8e5..f77895a 100644
--- a/src/mainboard/intel/wtm2/pei_data.c
+++ b/src/mainboard/intel/wtm2/pei_data.c
@@ -20,9 +20,9 @@
#include <stdint.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index 41bef93..d3ec418 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -21,10 +21,10 @@
#include <console/console.h>
#include <stdint.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
#include "gpio.h"
void mainboard_romstage_entry(struct romstage_params *rp)
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index b990e1b..ec6b9ae 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -70,7 +70,7 @@ romstage-y += usbdebug.c
smm-y += usbdebug.c
endif
-CPPFLAGS_common += -Isrc/soc/intel/broadwell/
+CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 5e7b72b..f038e87 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -34,14 +34,14 @@
#include <cpu/intel/turbo.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
-#include <broadwell/acpi.h>
-#include <broadwell/cpu.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/msr.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <chip.h>
+#include <soc/acpi.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/intel/broadwell/chip.h>
/*
* List of supported C-states in this processor. Only the ULT parts support C8,
diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl
index e40c042..998133d 100644
--- a/src/soc/intel/broadwell/acpi/pch.asl
+++ b/src/soc/intel/broadwell/acpi/pch.asl
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <soc/intel/broadwell/broadwell/iomap.h>
+#include <soc/iomap.h>
Scope (\)
{
diff --git a/src/soc/intel/broadwell/acpi/systemagent.asl b/src/soc/intel/broadwell/acpi/systemagent.asl
index 9c6dacd..8fcd0b7 100644
--- a/src/soc/intel/broadwell/acpi/systemagent.asl
+++ b/src/soc/intel/broadwell/acpi/systemagent.asl
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <soc/intel/broadwell/broadwell/iomap.h>
+#include <soc/iomap.h>
Name (_HID, EISAID ("PNP0A08")) // PCIe
Name (_CID, EISAID ("PNP0A03")) // PCI
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index bf77763..1a7cca7 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -25,14 +25,14 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include <delay.h>
-#include <broadwell/adsp.h>
-#include <broadwell/device_nvs.h>
-#include <broadwell/iobp.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pch.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
+#include <soc/adsp.h>
+#include <soc/device_nvs.h>
+#include <soc/iobp.h>
+#include <soc/nvs.h>
+#include <soc/pch.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
static void adsp_init(struct device *dev)
{
diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c
index 796f884..3a47d13 100644
--- a/src/soc/intel/broadwell/bootblock/cpu.c
+++ b/src/soc/intel/broadwell/bootblock/cpu.c
@@ -25,8 +25,8 @@
#include <arch/io.h>
#include <halt.h>
#include <cpu/intel/microcode/microcode.c>
-#include <broadwell/rcba.h>
-#include <broadwell/msr.h>
+#include <soc/rcba.h>
+#include <soc/msr.h>
static void set_var_mtrr(
unsigned reg, unsigned base, unsigned size, unsigned type)
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
index 2475a25..0115719 100644
--- a/src/soc/intel/broadwell/bootblock/pch.c
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -19,11 +19,11 @@
#include <arch/io.h>
#include <cpu/x86/tsc.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/rcba.h>
-#include <broadwell/spi.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
static void store_initial_timestamp(void)
{
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c
index b5f82b2..15e7fc8 100644
--- a/src/soc/intel/broadwell/bootblock/systemagent.c
+++ b/src/soc/intel/broadwell/bootblock/systemagent.c
@@ -18,8 +18,8 @@
*/
#include <arch/io.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/systemagent.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
static void bootblock_northbridge_init(void)
{
diff --git a/src/soc/intel/broadwell/broadwell/acpi.h b/src/soc/intel/broadwell/broadwell/acpi.h
deleted file mode 100644
index 63c0a36..0000000
--- a/src/soc/intel/broadwell/broadwell/acpi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_ACPI_H_
-#define _BROADWELL_ACPI_H_
-
-#include <arch/acpi.h>
-#include <broadwell/nvs.h>
-
-/* P-state configuration */
-#define PSS_MAX_ENTRIES 8
-#define PSS_RATIO_STEP 2
-#define PSS_LATENCY_TRANSITION 10
-#define PSS_LATENCY_BUSMASTER 10
-
-void acpi_create_intel_hpet(acpi_hpet_t *hpet);
-void acpi_fill_in_fadt(acpi_fadt_t *fadt);
-unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/adsp.h b/src/soc/intel/broadwell/broadwell/adsp.h
deleted file mode 100644
index 747a123..0000000
--- a/src/soc/intel/broadwell/broadwell/adsp.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_ADSP_H_
-#define _BROADWELL_ADSP_H_
-
-#define ADSP_PCI_IRQ 23
-#define ADSP_ACPI_IRQ 3
-#define ADSP_ACPI_IRQEN (1 << 3)
-
-#define ADSP_SHIM_BASE_LPT 0xe7000
-#define ADSP_SHIM_BASE_WPT 0xfb000
-#define ADSP_SHIM_LTRC 0xe0
-#define ADSP_SHIM_LTRC_VALUE 0x3003
-#define ADSP_SHIM_IMC 0x28
-#define ADSP_SHIM_IPCD 0x40
-
-#define ADSP_PCI_VDRTCTL0 0xa0
-#define ADSP_VDRTCTL0_D3PGD_LPT (1 << 1)
-#define ADSP_VDRTCTL0_D3PGD_WPT (1 << 0)
-#define ADSP_VDRTCTL0_D3SRAMPGD_LPT (1 << 2)
-#define ADSP_VDRTCTL0_D3SRAMPGD_WPT (1 << 1)
-#define ADSP_PCI_VDRTCTL1 0xa4
-#define ADSP_PCI_VDRTCTL2 0xa8
-#define ADSP_VDRTCTL2_VALUE 0x00000fff
-
-#define ADSP_IOBP_VDLDAT1 0xd7000624
-#define ADSP_VDLDAT1_VALUE 0x00040100
-#define ADSP_IOBP_VDLDAT2 0xd7000628
-#define ADSP_IOBP_ACPI_IRQ3 0xd9d8
-#define ADSP_IOBP_ACPI_IRQ3I 0xd8d9
-#define ADSP_IOBP_ACPI_IRQ4 0xdbda
-#define ADSP_IOBP_PMCTL 0xd70001e0
-#define ADSP_PMCTL_VALUE 0x3f
-#define ADSP_IOBP_PCICFGCTL 0xd7000500
-#define ADSP_PCICFGCTL_PCICD (1 << 0)
-#define ADSP_PCICFGCTL_ACPIIE (1 << 1)
-#define ADSP_PCICFGCTL_SPCBAD (1 << 7)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/cpu.h b/src/soc/intel/broadwell/broadwell/cpu.h
deleted file mode 100644
index 312532d..0000000
--- a/src/soc/intel/broadwell/broadwell/cpu.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_CPU_H_
-#define _BROADWELL_CPU_H_
-
-#include <arch/cpu.h>
-#include <device/device.h>
-
-/* CPU types */
-#define HASWELL_FAMILY_ULT 0x40650
-#define BROADWELL_FAMILY_ULT 0x306d0
-
-/* Supported CPUIDs */
-#define CPUID_HASWELL_A0 0x306c1
-#define CPUID_HASWELL_B0 0x306c2
-#define CPUID_HASWELL_C0 0x306c3
-#define CPUID_HASWELL_ULT_B0 0x40650
-#define CPUID_HASWELL_ULT 0x40651
-#define CPUID_HASWELL_HALO 0x40661
-#define CPUID_BROADWELL_C0 0x306d2
-#define CPUID_BROADWELL_D0 0x306d3
-#define CPUID_BROADWELL_E0 0x306d4
-
-/* CPU bus clock is fixed at 100MHz */
-#define CPU_BCLK 100
-
-/* Latency times in units of 1024ns. */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
-#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
-#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
-#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
-#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
-#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
-
-#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
- (((1 << ((base)*5)) * (limit)) / 1000)
-#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
- C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
- (IRTL_1024_NS >> 10))
-
-/* Configure power limits for turbo mode */
-void set_power_limits(u8 power_limit_1_time);
-int cpu_config_tdp_levels(void);
-
-/*
- * Determine if HyperThreading is disabled.
- * The variable is not valid until setup_ap_init() has been called.
- */
-extern int ht_disabled;
-
-/* CPU identification */
-u32 cpu_family_model(void);
-u32 cpu_stepping(void);
-int cpu_is_ult(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/device_nvs.h b/src/soc/intel/broadwell/broadwell/device_nvs.h
deleted file mode 100644
index 7dab40d..0000000
--- a/src/soc/intel/broadwell/broadwell/device_nvs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_DEVICE_NVS_H_
-#define _BROADWELL_DEVICE_NVS_H_
-
-#include <stdint.h>
-
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
-#define SIO_NVS_DMA 0
-#define SIO_NVS_I2C0 1
-#define SIO_NVS_I2C1 2
-#define SIO_NVS_SPI0 3
-#define SIO_NVS_SPI1 4
-#define SIO_NVS_UART0 5
-#define SIO_NVS_UART1 6
-#define SIO_NVS_SDIO 7
-#define SIO_NVS_ADSP 8
-
-typedef struct {
- u8 enable[9];
- u32 bar0[9];
- u32 bar1[9];
-} __attribute__((packed)) device_nvs_t;
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/ehci.h b/src/soc/intel/broadwell/broadwell/ehci.h
deleted file mode 100644
index 44d51ef..0000000
--- a/src/soc/intel/broadwell/broadwell/ehci.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_EHCI_H_
-#define _BROADWELL_EHCI_H_
-
-/* EHCI Memory Registers */
-#define EHCI_USB_CMD 0x20
-#define EHCI_USB_CMD_RUN (1 << 0)
-#define EHCI_USB_CMD_PSE (1 << 4)
-#define EHCI_USB_CMD_ASE (1 << 5)
-#define EHCI_PORTSC(port) (0x64 + (port * 4))
-#define EHCI_PORTSC_ENABLED (1 << 2)
-#define EHCI_PORTSC_SUSPEND (1 << 7)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/gpio.h b/src/soc/intel/broadwell/broadwell/gpio.h
deleted file mode 100644
index a035975..0000000
--- a/src/soc/intel/broadwell/broadwell/gpio.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_GPIO_H_
-#define _BROADWELL_GPIO_H_
-
-#include <stdint.h>
-
-/* PCH-LP GPIOBASE Registers */
-#define GPIO_OWNER(set) (0x00 + ((set) * 4))
-#define GPIO_PIRQ_APIC_EN 0x10
-#define GPIO_BLINK 0x18
-#define GPIO_SER_BLINK 0x1c
-#define GPIO_SER_BLINK_CS 0x20
-#define GPIO_SER_BLINK_DATA 0x24
-#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
-#define GPIO_ALT_GPI_SMI_STS 0x50
-#define GPIO_ALT_GPI_SMI_EN 0x54
-#define GPIO_RESET(set) (0x60 + ((set) * 4))
-#define GPIO_GLOBAL_CONFIG 0x7c
-#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
-#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4))
-#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8))
-#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
-
-#define MAX_GPIO_NUMBER 94 /* zero based */
-#define GPIO_LIST_END 0xffffffff
-
-/* conf0 */
-
-#define GPIO_MODE_NATIVE (0 << 0)
-#define GPIO_MODE_GPIO (1 << 0)
-
-#define GPIO_DIR_OUTPUT (0 << 2)
-#define GPIO_DIR_INPUT (1 << 2)
-
-#define GPIO_NO_INVERT (0 << 3)
-#define GPIO_INVERT (1 << 3)
-
-#define GPIO_IRQ_EDGE (0 << 4)
-#define GPIO_IRQ_LEVEL (1 << 4)
-
-#define GPI_LEVEL (1 << 30)
-
-#define GPIO_OUT_LOW 0
-#define GPIO_OUT_HIGH 1
-#define GPO_LEVEL_SHIFT 31
-#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_LOW (GPIO_OUT_LOW << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_HIGH (GPIO_OUT_HIGH << GPO_LEVEL_SHIFT)
-
-/* conf1 */
-
-#define GPIO_PULL_NONE (0 << 0)
-#define GPIO_PULL_DOWN (1 << 0)
-#define GPIO_PULL_UP (2 << 0)
-
-#define GPIO_SENSE_ENABLE (0 << 2)
-#define GPIO_SENSE_DISABLE (1 << 2)
-
-/* owner */
-
-#define GPIO_OWNER_ACPI 0
-#define GPIO_OWNER_GPIO 1
-
-/* route */
-
-#define GPIO_ROUTE_SCI 0
-#define GPIO_ROUTE_SMI 1
-
-/* irqen */
-
-#define GPIO_IRQ_DISABLE 0
-#define GPIO_IRQ_ENABLE 1
-
-/* blink */
-
-#define GPO_NO_BLINK 0
-#define GPO_BLINK 1
-
-/* reset */
-
-#define GPIO_RESET_PWROK 0
-#define GPIO_RESET_RSMRST 1
-
-/* pirq route to io-apic */
-
-#define GPIO_PIRQ_APIC_MASK 0
-#define GPIO_PIRQ_APIC_ROUTE 1
-
-#define PCH_GPIO_END \
- { .conf0 = GPIO_LIST_END }
-
-#define PCH_GPIO_NATIVE \
- { .conf0 = GPIO_MODE_NATIVE }
-
-#define PCH_GPIO_UNUSED \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
- .owner = GPIO_OWNER_GPIO, \
- .conf1 = GPIO_SENSE_DISABLE }
-
-#define PCH_GPIO_ACPI_SCI \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_ACPI, \
- .route = GPIO_ROUTE_SCI }
-
-#define PCH_GPIO_ACPI_SMI \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_ACPI, \
- .route = GPIO_ROUTE_SMI }
-
-#define PCH_GPIO_INPUT \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
- .owner = GPIO_OWNER_GPIO }
-
-#define PCH_GPIO_INPUT_INVERT \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
- .owner = GPIO_OWNER_GPIO }
-
-#define PCH_GPIO_IRQ_EDGE \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \
- .owner = GPIO_OWNER_GPIO, \
- .irqen = GPIO_IRQ_ENABLE }
-
-#define PCH_GPIO_IRQ_LEVEL \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \
- .owner = GPIO_OWNER_GPIO, \
- .irqen = GPIO_IRQ_ENABLE }
-
-#define PCH_GPIO_PIRQ \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
- .owner = GPIO_OWNER_GPIO, \
- .pirq = GPIO_PIRQ_APIC_ROUTE }
-
-#define PCH_GPIO_OUT_HIGH \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \
- .owner = GPIO_OWNER_GPIO, \
- .conf1 = GPIO_SENSE_DISABLE }
-
-#define PCH_GPIO_OUT_LOW \
- { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \
- .owner = GPIO_OWNER_GPIO, \
- .conf1 = GPIO_SENSE_DISABLE }
-
-struct gpio_config {
- u8 gpio;
- u32 conf0;
- u32 conf1;
- u8 owner;
- u8 route;
- u8 irqen;
- u8 reset;
- u8 blink;
- u8 pirq;
-} __attribute__ ((packed));
-
-/* Configure GPIOs with mainboard provided settings */
-void init_one_gpio(int gpio_num, struct gpio_config *config);
-void init_gpios(const struct gpio_config config[]);
-
-/* Get GPIO pin value */
-int get_gpio(int gpio_num);
-
-/* Set GPIO pin value */
-void set_gpio(int gpio_num, int value);
-
-/* Return non-zero if gpio is set to native function. 0 otherwise. */
-int gpio_is_native(int gpio_num);
-
-/*
- * Get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned get_gpios(const int *gpio_num_array);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/iobp.h b/src/soc/intel/broadwell/broadwell/iobp.h
deleted file mode 100644
index 9f17692..0000000
--- a/src/soc/intel/broadwell/broadwell/iobp.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_IOBP_H_
-#define _BROADWELL_IOBP_H_
-
-u32 pch_iobp_read(u32 address);
-void pch_iobp_write(u32 address, u32 data);
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/iomap.h b/src/soc/intel/broadwell/broadwell/iomap.h
deleted file mode 100644
index bb98975..0000000
--- a/src/soc/intel/broadwell/broadwell/iomap.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_IOMAP_H_
-#define _BROADWELL_IOMAP_H_
-
-#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
-#define MCFG_BASE_SIZE 0x4000000
-
-#define MCH_BASE_ADDRESS 0xfed10000
-#define MCH_BASE_SIZE 0x8000
-
-#define DMI_BASE_ADDRESS 0xfed18000
-#define DMI_BASE_SIZE 0x1000
-
-#define EP_BASE_ADDRESS 0xfed19000
-#define EP_BASE_SIZE 0x1000
-
-#define EDRAM_BASE_ADDRESS 0xfed80000
-#define EDRAM_BASE_SIZE 0x4000
-
-#define GDXC_BASE_ADDRESS 0xfed84000
-#define GDXC_BASE_SIZE 0x1000
-
-#define RCBA_BASE_ADDRESS 0xfed1c000
-#define RCBA_BASE_SIZE 0x4000
-
-#define HPET_BASE_ADDRESS 0xfed00000
-
-#define ACPI_BASE_ADDRESS 0x1000
-#define ACPI_BASE_SIZE 0x100
-
-#define GPIO_BASE_ADDRESS 0x1400
-#define GPIO_BASE_SIZE 0x400
-
-#define SMBUS_BASE_ADDRESS 0x0400
-#define SMBUS_BASE_SIZE 0x10
-
-/* Temporary addresses used in romstage */
-#define EARLY_GTT_BAR 0xe0000000
-#define EARLY_XHCI_BAR 0xd7000000
-#define EARLY_EHCI_BAR CONFIG_EHCI_BAR
-#define EARLY_UART_BAR CONFIG_TTYS0_BASE
-#define EARLY_TEMP_MMIO 0xfed08000
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/lpc.h b/src/soc/intel/broadwell/broadwell/lpc.h
deleted file mode 100644
index 180e527..0000000
--- a/src/soc/intel/broadwell/broadwell/lpc.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_LPC_H_
-#define _BROADWELL_LPC_H_
-
-/* PCI Configuration Space (D31:F0): LPC */
-#define SERIRQ_CNTL 0x64
-#define PMBASE 0x40
-#define ACPI_CNTL 0x44
-#define ACPI_EN (1 << 7)
-#define SCI_IRQ_SEL (7 << 0)
-#define SCIS_IRQ9 0
-#define SCIS_IRQ10 1
-#define SCIS_IRQ11 2
-#define SCIS_IRQ20 4
-#define SCIS_IRQ21 5
-#define SCIS_IRQ22 6
-#define SCIS_IRQ23 7
-#define GPIOBASE 0x48
-#define BIOS_CNTL 0xdc
-#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
-#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
-#define GPIO_EN (1 << 4)
-#define GPIO_ROUT 0xb8
-
-#define PIRQA_ROUT 0x60
-#define PIRQB_ROUT 0x61
-#define PIRQC_ROUT 0x62
-#define PIRQD_ROUT 0x63
-#define PIRQE_ROUT 0x68
-#define PIRQF_ROUT 0x69
-#define PIRQG_ROUT 0x6A
-#define PIRQH_ROUT 0x6B
-
-#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
-#define LPC_EN 0x82 /* LPC IF Enables Register */
-#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
-#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
-#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
-#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
-#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
-#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
-#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
-#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
-#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
-#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
-#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
-#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
-#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
-#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
-#define LGMR 0x98 /* LPC Generic Memory Range */
-#define RCBA 0xf0 /* Root Complex Register Block */
-
-/* Power Management */
-
-#define GEN_PMCON_1 0xa0
-#define SMI_LOCK (1 << 4)
-#define GEN_PMCON_2 0xa2
-#define SYSTEM_RESET_STS (1 << 4)
-#define THERMTRIP_STS (1 << 3)
-#define SYSPWR_FLR (1 << 1)
-#define PWROK_FLR (1 << 0)
-#define GEN_PMCON_3 0xa4
-#define SUS_PWR_FLR (1 << 14)
-#define GEN_RST_STS (1 << 9)
-#define RTC_BATTERY_DEAD (1 << 2)
-#define PWR_FLR (1 << 1)
-#define SLEEP_AFTER_POWER_FAIL (1 << 0)
-#define GEN_PMCON_LOCK 0xa6
-#define SLP_STR_POL_LOCK (1 << 2)
-#define ACPI_BASE_LOCK (1 << 1)
-#define PMIR 0xac
-#define PMIR_CF9LOCK (1 << 31)
-#define PMIR_CF9GR (1 << 20)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h
deleted file mode 100644
index a69dfd5..0000000
--- a/src/soc/intel/broadwell/broadwell/me.h
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_ME_H_
-#define _BROADWELL_ME_H_
-
-#include <console/loglevel.h>
-
-#define ME_RETRY 100000 /* 1 second */
-#define ME_DELAY 10 /* 10 us */
-
-/*
- * Management Engine PCI registers
- */
-
-#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
-#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
-
-#define PCI_ME_HFS 0x40
-#define ME_HFS_CWS_RESET 0
-#define ME_HFS_CWS_INIT 1
-#define ME_HFS_CWS_REC 2
-#define ME_HFS_CWS_NORMAL 5
-#define ME_HFS_CWS_WAIT 6
-#define ME_HFS_CWS_TRANS 7
-#define ME_HFS_CWS_INVALID 8
-#define ME_HFS_STATE_PREBOOT 0
-#define ME_HFS_STATE_M0_UMA 1
-#define ME_HFS_STATE_M3 4
-#define ME_HFS_STATE_M0 5
-#define ME_HFS_STATE_BRINGUP 6
-#define ME_HFS_STATE_ERROR 7
-#define ME_HFS_ERROR_NONE 0
-#define ME_HFS_ERROR_UNCAT 1
-#define ME_HFS_ERROR_IMAGE 3
-#define ME_HFS_ERROR_DEBUG 4
-#define ME_HFS_MODE_NORMAL 0
-#define ME_HFS_MODE_DEBUG 2
-#define ME_HFS_MODE_DIS 3
-#define ME_HFS_MODE_OVER_JMPR 4
-#define ME_HFS_MODE_OVER_MEI 5
-#define ME_HFS_BIOS_DRAM_ACK 1
-#define ME_HFS_ACK_NO_DID 0
-#define ME_HFS_ACK_RESET 1
-#define ME_HFS_ACK_PWR_CYCLE 2
-#define ME_HFS_ACK_S3 3
-#define ME_HFS_ACK_S4 4
-#define ME_HFS_ACK_S5 5
-#define ME_HFS_ACK_GBL_RESET 6
-#define ME_HFS_ACK_CONTINUE 7
-
-struct me_hfs {
- u32 working_state: 4;
- u32 mfg_mode: 1;
- u32 fpt_bad: 1;
- u32 operation_state: 3;
- u32 fw_init_complete: 1;
- u32 ft_bup_ld_flr: 1;
- u32 update_in_progress: 1;
- u32 error_code: 4;
- u32 operation_mode: 4;
- u32 reserved: 4;
- u32 boot_options_present: 1;
- u32 ack_data: 3;
- u32 bios_msg_ack: 4;
-} __attribute__ ((packed));
-
-#define PCI_ME_UMA 0x44
-
-struct me_uma {
- u32 size: 6;
- u32 reserved_1: 10;
- u32 valid: 1;
- u32 reserved_0: 14;
- u32 set_to_one: 1;
-} __attribute__ ((packed));
-
-#define PCI_ME_H_GS 0x4c
-#define ME_INIT_DONE 1
-#define ME_INIT_STATUS_SUCCESS 0
-#define ME_INIT_STATUS_NOMEM 1
-#define ME_INIT_STATUS_ERROR 2
-#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
-
-#define ME_HSIO_MESSAGE (7 << 28)
-#define ME_HSIO_CMD_GETHSIOVER 1
-#define ME_HSIO_CMD_CLOSE 0
-
-struct me_did {
- u32 uma_base: 16;
- u32 reserved: 7;
- u32 rapid_start: 1;
- u32 status: 4;
- u32 init_done: 4;
-} __attribute__ ((packed));
-
-/*
- * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
- * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
- */
-#define PCI_ME_HFS2 0x48
-/* Infrastructure Progress Values */
-#define ME_HFS2_PHASE_ROM 0
-#define ME_HFS2_PHASE_BUP 1
-#define ME_HFS2_PHASE_UKERNEL 2
-#define ME_HFS2_PHASE_POLICY 3
-#define ME_HFS2_PHASE_MODULE_LOAD 4
-#define ME_HFS2_PHASE_UNKNOWN 5
-#define ME_HFS2_PHASE_HOST_COMM 6
-/* Current State - Based on Infra Progress values. */
-/* ROM State */
-#define ME_HFS2_STATE_ROM_BEGIN 0
-#define ME_HFS2_STATE_ROM_DISABLE 6
-/* BUP State */
-#define ME_HFS2_STATE_BUP_INIT 0
-#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
-#define ME_HFS2_STATE_BUP_FLOW_DET 4
-#define ME_HFS2_STATE_BUP_VSCC_ERR 8
-#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
-#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
-#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
-#define ME_HFS2_STATE_BUP_M3 0x11
-#define ME_HFS2_STATE_BUP_M0 0x12
-#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
-#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
-#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
-#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
-#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
-#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
-#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
-#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
-#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
-#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
-#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
-#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
-#define ME_HFS2_STATE_BUP_M0_CLK 0x26
-#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
-#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
-#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
-/* Policy Module State */
-#define ME_HFS2_STATE_POLICY_ENTRY 0
-#define ME_HFS2_STATE_POLICY_RCVD_S3 3
-#define ME_HFS2_STATE_POLICY_RCVD_S4 4
-#define ME_HFS2_STATE_POLICY_RCVD_S5 5
-#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
-#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
-#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
-#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
-#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
-#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
-#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
-#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
-#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
-#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
-#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
-/* Current PM Event Values */
-#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
-#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
-#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
-#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
-#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
-#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
-#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
-#define ME_HFS2_PMEVENT_S0MO_SXM3 7
-#define ME_HFS2_PMEVENT_SXM3_S0M0 8
-#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
-#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
-#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
-#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
-
-struct me_hfs2 {
- u32 bist_in_progress: 1;
- u32 reserved1: 2;
- u32 invoke_mebx: 1;
- u32 cpu_replaced_sts: 1;
- u32 mbp_rdy: 1;
- u32 mfs_failure: 1;
- u32 warm_reset_request: 1;
- u32 cpu_replaced_valid: 1;
- u32 reserved2: 4;
- u32 mbp_cleared: 1;
- u32 reserved3: 2;
- u32 current_state: 8;
- u32 current_pmevent: 4;
- u32 progress_code: 4;
-} __attribute__ ((packed));
-
-#define PCI_ME_HFS5 0x68
-
-#define PCI_ME_H_GS2 0x70
-#define PCI_ME_MBP_GIVE_UP 0x01
-
-#define PCI_ME_HERES 0xbc
-#define PCI_ME_EXT_SHA1 0x00
-#define PCI_ME_EXT_SHA256 0x02
-#define PCI_ME_HER(x) (0xc0+(4*(x)))
-
-struct me_heres {
- u32 extend_reg_algorithm: 4;
- u32 reserved: 26;
- u32 extend_feature_present: 1;
- u32 extend_reg_valid: 1;
-} __attribute__ ((packed));
-
-/*
- * Management Engine MEI registers
- */
-
-#define MEI_H_CB_WW 0x00
-#define MEI_H_CSR 0x04
-#define MEI_ME_CB_RW 0x08
-#define MEI_ME_CSR_HA 0x0c
-
-struct mei_csr {
- u32 interrupt_enable: 1;
- u32 interrupt_status: 1;
- u32 interrupt_generate: 1;
- u32 ready: 1;
- u32 reset: 1;
- u32 reserved: 3;
- u32 buffer_read_ptr: 8;
- u32 buffer_write_ptr: 8;
- u32 buffer_depth: 8;
-} __attribute__ ((packed));
-
-#define MEI_ADDRESS_CORE 0x01
-#define MEI_ADDRESS_AMT 0x02
-#define MEI_ADDRESS_RESERVED 0x03
-#define MEI_ADDRESS_WDT 0x04
-#define MEI_ADDRESS_MKHI 0x07
-#define MEI_ADDRESS_ICC 0x08
-#define MEI_ADDRESS_THERMAL 0x09
-
-#define MEI_HOST_ADDRESS 0
-
-struct mei_header {
- u32 client_address: 8;
- u32 host_address: 8;
- u32 length: 9;
- u32 reserved: 6;
- u32 is_complete: 1;
-} __attribute__ ((packed));
-
-#define MKHI_GROUP_ID_CBM 0x00
-#define MKHI_GROUP_ID_FWCAPS 0x03
-#define MKHI_GROUP_ID_MDES 0x08
-#define MKHI_GROUP_ID_GEN 0xff
-
-#define MKHI_GLOBAL_RESET 0x0b
-
-#define MKHI_FWCAPS_GET_RULE 0x02
-
-#define MKHI_MDES_ENABLE 0x09
-
-#define MKHI_GET_FW_VERSION 0x02
-#define MKHI_END_OF_POST 0x0c
-#define MKHI_FEATURE_OVERRIDE 0x14
-
-struct mkhi_header {
- u32 group_id: 8;
- u32 command: 7;
- u32 is_response: 1;
- u32 reserved: 8;
- u32 result: 8;
-} __attribute__ ((packed));
-
-struct me_fw_version {
- u16 code_minor;
- u16 code_major;
- u16 code_build_number;
- u16 code_hot_fix;
- u16 recovery_minor;
- u16 recovery_major;
- u16 recovery_build_number;
- u16 recovery_hot_fix;
-} __attribute__ ((packed));
-
-/* ICC Messages */
-#define ICC_SET_CLOCK_ENABLES 0x3
-#define ICC_API_VERSION_LYNXPOINT 0x00030000
-
-struct icc_header {
- u32 api_version;
- u32 icc_command;
- u32 icc_status;
- u32 length;
- u32 reserved;
-} __attribute__ ((packed));
-
-struct icc_clock_enables_msg {
- u32 clock_enables;
- u32 clock_mask;
- u32 no_response: 1;
- u32 reserved: 31;
-} __attribute__ ((packed));
-
-#define HECI_EOP_STATUS_SUCCESS 0x0
-#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
-
-#define CBM_RR_GLOBAL_RESET 0x01
-
-#define GLOBAL_RESET_BIOS_MRC 0x01
-#define GLOBAL_RESET_BIOS_POST 0x02
-#define GLOBAL_RESET_MEBX 0x03
-
-struct me_global_reset {
- u8 request_origin;
- u8 reset_type;
-} __attribute__ ((packed));
-
-typedef enum {
- ME_NORMAL_BIOS_PATH,
- ME_S3WAKE_BIOS_PATH,
- ME_ERROR_BIOS_PATH,
- ME_RECOVERY_BIOS_PATH,
- ME_DISABLE_BIOS_PATH,
- ME_FIRMWARE_UPDATE_BIOS_PATH,
-} me_bios_path;
-
-/*
- * ME to BIOS Payload Datastructures and definitions. The ordering of the
- * structures follows the ordering in the ME9 BWG.
- */
-
-#define MBP_APPID_KERNEL 1
-#define MBP_APPID_INTEL_AT 3
-#define MBP_APPID_HWA 4
-#define MBP_APPID_ICC 5
-#define MBP_APPID_NFC 6
-/* Kernel items: */
-#define MBP_KERNEL_FW_VER_ITEM 1
-#define MBP_KERNEL_FW_CAP_ITEM 2
-#define MBP_KERNEL_ROM_BIST_ITEM 3
-#define MBP_KERNEL_PLAT_KEY_ITEM 4
-#define MBP_KERNEL_FW_TYPE_ITEM 5
-#define MBP_KERNEL_MFS_FAILURE_ITEM 6
-#define MBP_KERNEL_PLAT_TIME_ITEM 7
-/* Intel AT items: */
-#define MBP_INTEL_AT_STATE_ITEM 1
-/* ICC Items: */
-#define MBP_ICC_PROFILE_ITEM 1
-/* HWA Items: */
-#define MBP_HWA_REQUEST_ITEM 1
-/* NFC Items: */
-#define MBP_NFC_SUPPORT_DATA_ITEM 1
-
-#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
-#define MBP_IDENT(appid, item) \
- MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
-
-typedef struct {
- u32 mbp_size : 8;
- u32 num_entries : 8;
- u32 rsvd : 16;
-} __attribute__ ((packed)) mbp_header;
-
-typedef struct {
- u32 app_id : 8;
- u32 item_id : 8;
- u32 length : 8;
- u32 rsvd : 8;
-} __attribute__ ((packed)) mbp_item_header;
-
-typedef struct {
- u32 major_version : 16;
- u32 minor_version : 16;
- u32 hotfix_version : 16;
- u32 build_version : 16;
-} __attribute__ ((packed)) mbp_fw_version_name;
-
-typedef struct {
- u32 full_net : 1;
- u32 std_net : 1;
- u32 manageability : 1;
- u32 reserved_2 : 2;
- u32 intel_at : 1;
- u32 intel_cls : 1;
- u32 reserved : 3;
- u32 intel_mpc : 1;
- u32 icc_over_clocking : 1;
- u32 pavp : 1;
- u32 reserved_1 : 4;
- u32 ipv6 : 1;
- u32 kvm : 1;
- u32 och : 1;
- u32 vlan : 1;
- u32 tls : 1;
- u32 reserved_4 : 1;
- u32 wlan : 1;
- u32 reserved_5 : 8;
-} __attribute__ ((packed)) mbp_mefwcaps;
-
-typedef struct {
- u16 device_id;
- u16 fuse_test_flags;
- u32 umchid[4];
-} __attribute__ ((packed)) mbp_rom_bist_data;
-
-typedef struct {
- u32 key[8];
-} mbp_platform_key;
-
-typedef struct {
- u32 mobile: 1;
- u32 desktop: 1;
- u32 server: 1;
- u32 workstation: 1;
- u32 corporate: 1;
- u32 consumer: 1;
- u32 regular_super_sku: 1;
- u32 rsvd: 1;
- u32 image_type: 4;
- u32 brand: 4;
- u32 rsvd1: 16;
-} __attribute__ ((packed)) mbp_me_firmware_type;
-
-typedef struct {
- mbp_me_firmware_type rule_data;
- u8 available;
-} mbp_plat_type;
-
-typedef struct {
- u16 icc_start_address;
- u16 mask;
-} __attribute__ ((packed)) icc_address_mask;
-
-typedef struct {
- u8 num_icc_profiles;
- u8 icc_profile_soft_strap;
- u8 icc_profile_index;
- u8 reserved;
- u32 icc_reg_bundles;
- icc_address_mask icc_address_mask[0];
-} __attribute__ ((packed)) mbp_icc_profile;
-
-typedef struct {
- u16 lock_state : 1;
- u16 authenticate_module : 1;
- u16 s3authentication : 1;
- u16 flash_wear_out : 1;
- u16 flash_variable_security : 1;
- u16 reserved : 11;
-} __attribute__ ((packed)) tdt_state_flag;
-
-typedef struct {
- u8 state;
- u8 last_theft_trigger;
- tdt_state_flag flags;
-} __attribute__ ((packed)) mbp_at_state;
-
-typedef struct {
- u32 wake_event_mrst_time_ms;
- u32 mrst_pltrst_time_ms;
- u32 pltrst_cpurst_time_ms;
-} __attribute__ ((packed)) mbp_plat_time;
-
-typedef struct {
- u32 device_type : 2;
- u32 reserved : 30;
-} __attribute__ ((packed)) mbp_nfc_data;
-
-typedef struct {
- mbp_fw_version_name *fw_version_name;
- mbp_mefwcaps *fw_capabilities;
- mbp_rom_bist_data *rom_bist_data;
- mbp_platform_key *platform_key;
- mbp_plat_type *fw_plat_type;
- mbp_icc_profile *icc_profile;
- mbp_at_state *at_state;
- u32 *mfsintegrity;
- mbp_plat_time *plat_time;
- mbp_nfc_data *nfc_data;
-} me_bios_payload;
-
-struct me_fwcaps {
- u32 id;
- u8 length;
- mbp_mefwcaps caps_sku;
- u8 reserved[3];
-} __attribute__ ((packed));
-
-void intel_me_finalize(void);
-void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
-
-#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
-/* Defined in me_status.c for both romstage and ramstage */
-void intel_me_status(void);
-#else
-static inline void intel_me_status(void) { }
-#endif
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/msr.h b/src/soc/intel/broadwell/broadwell/msr.h
deleted file mode 100644
index 707041a..0000000
--- a/src/soc/intel/broadwell/broadwell/msr.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_MSR_H_
-#define _BROADWELL_MSR_H_
-
-#define MSR_PIC_MSG_CONTROL 0x2e
-#define CORE_THREAD_COUNT_MSR 0x35
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
-#define MSR_PLATFORM_INFO 0xce
-#define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
-#define MSR_PMG_IO_CAPTURE_BASE 0xe4
-#define MSR_FEATURE_CONFIG 0x13c
-#define SMM_MCA_CAP_MSR 0x17d
-#define SMM_CPU_SVRSTR_BIT 57
-#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
-#define MSR_FLEX_RATIO 0x194
-#define FLEX_RATIO_LOCK (1 << 20)
-#define FLEX_RATIO_EN (1 << 16)
-#define IA32_MISC_ENABLE 0x1a0
-#define MSR_MISC_PWR_MGMT 0x1aa
-#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
-#define MSR_TURBO_RATIO_LIMIT 0x1ad
-#define MSR_TEMPERATURE_TARGET 0x1a2
-#define IA32_PERF_CTL 0x199
-#define IA32_THERM_INTERRUPT 0x19b
-#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
-#define ENERGY_POLICY_PERFORMANCE 0
-#define ENERGY_POLICY_NORMAL 6
-#define ENERGY_POLICY_POWERSAVE 15
-#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
-#define EMRRphysBase_MSR 0x1f4
-#define EMRRphysMask_MSR 0x1f5
-#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define MSR_POWER_CTL 0x1fc
-#define MSR_LT_LOCK_MEMORY 0x2e7
-#define UNCORE_EMRRphysBase_MSR 0x2f4
-#define UNCORE_EMRRphysMask_MSR 0x2f5
-#define IA32_MC0_STATUS 0x401
-#define SMM_FEATURE_CONTROL_MSR 0x4e0
-#define SMM_CPU_SAVE_EN (1 << 1)
-
-#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
-#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
-#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
-#define MSR_C_STATE_LATENCY_CONTROL_3 0x633
-#define MSR_C_STATE_LATENCY_CONTROL_4 0x634
-#define MSR_C_STATE_LATENCY_CONTROL_5 0x635
-#define IRTL_VALID (1 << 15)
-#define IRTL_1_NS (0 << 10)
-#define IRTL_32_NS (1 << 10)
-#define IRTL_1024_NS (2 << 10)
-#define IRTL_32768_NS (3 << 10)
-#define IRTL_1048576_NS (4 << 10)
-#define IRTL_33554432_NS (5 << 10)
-#define IRTL_RESPONSE_MASK (0x3ff)
-#define MSR_COUNTER_24_MHZ 0x637
-
-/* long duration in low dword, short duration in high dword */
-#define MSR_PKG_POWER_LIMIT 0x610
-#define PKG_POWER_LIMIT_MASK 0x7fff
-#define PKG_POWER_LIMIT_EN (1 << 15)
-#define PKG_POWER_LIMIT_CLAMP (1 << 16)
-#define PKG_POWER_LIMIT_TIME_SHIFT 17
-#define PKG_POWER_LIMIT_TIME_MASK 0x7f
-
-#define MSR_VR_CURRENT_CONFIG 0x601
-#define MSR_VR_MISC_CONFIG 0x603
-#define MSR_PKG_POWER_SKU_UNIT 0x606
-#define MSR_PKG_POWER_SKU 0x614
-#define MSR_DDR_RAPL_LIMIT 0x618
-#define MSR_VR_MISC_CONFIG2 0x636
-#define MSR_PP0_POWER_LIMIT 0x638
-#define MSR_PP1_POWER_LIMIT 0x640
-
-#define MSR_CONFIG_TDP_NOMINAL 0x648
-#define MSR_CONFIG_TDP_LEVEL1 0x649
-#define MSR_CONFIG_TDP_LEVEL2 0x64a
-#define MSR_CONFIG_TDP_CONTROL 0x64b
-#define MSR_TURBO_ACTIVATION_RATIO 0x64c
-
-/* SMM save state MSRs */
-#define SMBASE_MSR 0xc20
-#define IEDBASE_MSR 0xc22
-
-/* MTRRcap_MSR bits */
-#define SMRR_SUPPORTED (1<<11)
-#define EMRR_SUPPORTED (1<<12)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/nvs.h b/src/soc/intel/broadwell/broadwell/nvs.h
deleted file mode 100644
index 398e0a2..0000000
--- a/src/soc/intel/broadwell/broadwell/nvs.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_NVS_H_
-#define _BROADWELL_NVS_H_
-
-#include <vendorcode/google/chromeos/gnvs.h>
-#include <broadwell/device_nvs.h>
-
-typedef struct {
- /* Miscellaneous */
- u16 osys; /* 0x00 - Operating System */
- u8 smif; /* 0x02 - SMI function call ("TRAP") */
- u8 prm0; /* 0x03 - SMI function call parameter */
- u8 prm1; /* 0x04 - SMI function call parameter */
- u8 scif; /* 0x05 - SCI function call (via _L00) */
- u8 prm2; /* 0x06 - SCI function call parameter */
- u8 prm3; /* 0x07 - SCI function call parameter */
- u8 lckf; /* 0x08 - Global Lock function for EC */
- u8 prm4; /* 0x09 - Lock function parameter */
- u8 prm5; /* 0x0a - Lock function parameter */
- u8 pcnt; /* 0x0b - Processor Count */
- u8 ppcm; /* 0x0c - Max PPC State */
- u8 tmps; /* 0x0d - Temperature Sensor ID */
- u8 tlvl; /* 0x0e - Throttle Level Limit */
- u8 flvl; /* 0x0f - Current FAN Level */
- u8 tcrt; /* 0x10 - Critical Threshold */
- u8 tpsv; /* 0x11 - Passive Threshold */
- u8 tmax; /* 0x12 - CPU Tj_max */
- u8 tpmp; /* 0x13 - TPM Present */
- u8 s5u0; /* 0x14 - Enable USB in S5 */
- u8 s3u0; /* 0x15 - Enable USB in S3 */
- u8 s33g; /* 0x16 - Enable 3G in S3 */
- u8 lids; /* 0x17 - LID State */
- u8 pwrs; /* 0x18 - AC Power State */
- u32 obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */
- u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
- u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
- u8 rsvd3[219];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
-
- /* Device specific (0x1000) */
- device_nvs_t dev;
-} __attribute__((packed)) global_nvs_t;
-
-void acpi_create_gnvs(global_nvs_t *gnvs);
-#ifdef __SMM__
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-#endif
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h
deleted file mode 100644
index e677215..0000000
--- a/src/soc/intel/broadwell/broadwell/pch.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_PCH_H_
-#define _BROADWELL_PCH_H_
-
-/* Haswell ULT Pch (LynxPoint-LP) */
-#define PCH_LPT_LP_SAMPLE 0x9c41
-#define PCH_LPT_LP_PREMIUM 0x9c43
-#define PCH_LPT_LP_MAINSTREAM 0x9c45
-#define PCH_LPT_LP_VALUE 0x9c47
-
-/* Broadwell PCH (WildatPoint) */
-#define PCH_WPT_HSW_U_SAMPLE 0x9cc1
-#define PCH_WPT_BDW_U_SAMPLE 0x9cc2
-#define PCH_WPT_BDW_U_PREMIUM 0x9cc3
-#define PCH_WPT_BDW_U_BASE 0x9cc5
-#define PCH_WPT_BDW_Y_SAMPLE 0x9cc6
-#define PCH_WPT_BDW_Y_PREMIUM 0x9cc7
-#define PCH_WPT_BDW_Y_BASE 0x9cc9
-#define PCH_WPT_BDW_H 0x9ccb
-
-/* Power Management Control and Status */
-#define PCH_PCS 0x84
-#define PCH_PCS_PS_D3HOT 3
-
-u8 pch_revision(void);
-u16 pch_type(void);
-int pch_is_wpt(void);
-int pch_is_wpt_ulx(void);
-u32 pch_read_soft_strap(int id);
-void pch_log_state(void);
-void pch_disable_devfn(device_t dev);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/pci_devs.h b/src/soc/intel/broadwell/broadwell/pci_devs.h
deleted file mode 100644
index 76e3a68..0000000
--- a/src/soc/intel/broadwell/broadwell/pci_devs.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_PCI_DEVS_H_
-#define _BROADWELL_PCI_DEVS_H_
-
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEVFN(slot,func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
-
-#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
-#include <arch/io.h>
-#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
-#define _PCH_DEV(slot,func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
-#else
-#include <device/device.h>
-#include <device/pci_def.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot,func) dev_find_slot(0, _PCH_DEVFN(slot, func))
-#endif
-
-/* System Agent Devices */
-
-#define SA_DEV_SLOT_ROOT 0x00
-#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
-#define SA_DEV_ROOT _SA_DEV(ROOT)
-
-#define SA_DEV_SLOT_IGD 0x02
-#define SA_DEVFN_IGD _SA_DEVFN(IGD)
-#define SA_DEV_IGD _SA_DEV(IGD)
-
-#define SA_DEV_SLOT_MINIHD 0x03
-#define SA_DEVFN_MINIHD _SA_DEVFN(MINIHD)
-#define SA_DEV_MINIHD _SA_DEV(MINIHD)
-
-/* PCH Devices */
-
-#define PCH_DEV_SLOT_ADSP 0x13
-#define PCH_DEVFN_ADSP _PCH_DEVFN(ADSP, 0)
-#define PCH_DEV_ADSP _PCH_DEV(ADSP, 0)
-
-#define PCH_DEV_SLOT_XHCI 0x14
-#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
-#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
-
-#define PCH_DEV_SLOT_SIO 0x15
-#define PCH_DEV_SDMA _PCH_DEV(SIO, 0)
-#define PCH_DEV_I2C0 _PCH_DEV(SIO, 1)
-#define PCH_DEV_I2C1 _PCH_DEV(SIO, 2)
-#define PCH_DEV_SPI0 _PCH_DEV(SIO, 3)
-#define PCH_DEV_SPI1 _PCH_DEV(SIO, 4)
-#define PCH_DEV_UART0 _PCH_DEV(SIO, 5)
-#define PCH_DEV_UART1 _PCH_DEV(SIO, 6)
-#define PCH_DEVFN_SDMA _PCH_DEVFN(SIO, 0)
-#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO, 1)
-#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO, 2)
-#define PCH_DEVFN_SPI0 _PCH_DEVFN(SIO, 3)
-#define PCH_DEVFN_SPI1 _PCH_DEVFN(SIO, 4)
-#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO, 5)
-#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO, 6)
-
-#define PCH_DEV_SLOT_ME 0x16
-#define PCH_DEVFN_ME _PCH_DEVFN(ME, 0)
-#define PCH_DEVFN_ME_2 _PCH_DEVFN(ME, 1)
-#define PCH_DEVFN_ME_IDER _PCH_DEVFN(ME, 2)
-#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3)
-#define PCH_DEV_ME _PCH_DEV(ME, 0)
-#define PCH_DEV_ME_2 _PCH_DEV(ME, 1)
-#define PCH_DEV_ME_IDER _PCH_DEV(ME, 2)
-#define PCH_DEV_ME_KT _PCH_DEV(ME, 3)
-
-#define PCH_DEV_SLOT_SDIO 0x17
-#define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0)
-#define PCH_DEV_SDIO _PCH_DEV(SDIO, 0)
-
-#define PCH_DEV_SLOT_GBE 0x19
-#define PCH_DEVFN_GBE _PCH_DEVFN(GBE, 0)
-#define PCH_DEV_GBE _PCH_DEV(GBE, 0)
-
-#define PCH_DEV_SLOT_HDA 0x1b
-#define PCH_DEVFN_HDA _PCH_DEVFN(HDA, 0)
-#define PCH_DEV_HDA _PCH_DEV(HDA, 0)
-
-#define PCH_DEV_SLOT_PCIE 0x1c
-
-#define PCH_DEV_SLOT_EHCI 0x1d
-#define PCH_DEVFN_EHCI _PCH_DEVFN(EHCI, 0)
-#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0)
-
-#define PCH_DEV_SLOT_LPC 0x1f
-#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
-#define PCH_DEVFN_IDE _PCH_DEVFN(LPC, 1)
-#define PCH_DEVFN_SATA _PCH_DEVFN(LPC, 2)
-#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 3)
-#define PCH_DEVFN_SATA2 _PCH_DEVFN(LPC, 5)
-#define PCH_DEVFN_THERMAL _PCH_DEVFN(LPC, 6)
-#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
-#define PCH_DEV_IDE _PCH_DEV(LPC, 1)
-#define PCH_DEV_SATA _PCH_DEV(LPC, 2)
-#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3)
-#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5)
-#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/pei_data.h b/src/soc/intel/broadwell/broadwell/pei_data.h
deleted file mode 100644
index e614718..0000000
--- a/src/soc/intel/broadwell/broadwell/pei_data.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Broadwell UEFI PEI wrapper
- *
- * Copyright (C) 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Google Inc. nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef PEI_DATA_H
-#define PEI_DATA_H
-
-#include <types.h>
-#include <memory_info.h>
-
-#define PEI_VERSION 22
-
-#define ABI_X86 __attribute__((regparm(0)))
-
-typedef void ABI_X86 (*tx_byte_func)(unsigned char byte);
-
-enum board_type {
- BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
- BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
- BOARD_TYPE_USER1, /* SV mobile */
- BOARD_TYPE_USER2, /* SV desktop */
- BOARD_TYPE_USER3, /* SV server */
- BOARD_TYPE_ULT, /* ULT */
- BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
- BOARD_TYPE_UNKNOWN,
-};
-
-#define MAX_USB2_PORTS 14
-#define MAX_USB3_PORTS 6
-#define USB_OC_PIN_SKIP 8
-
-enum usb2_port_location {
- USB_PORT_BACK_PANEL = 0,
- USB_PORT_FRONT_PANEL,
- USB_PORT_DOCK,
- USB_PORT_MINI_PCIE,
- USB_PORT_FLEX,
- USB_PORT_INTERNAL,
- USB_PORT_SKIP,
- USB_PORT_NGFF_DEVICE_DOWN,
-};
-
-struct usb2_port_setting {
- /*
- * Usb Port Length:
- * [16:4] = length in inches in octal format
- * [3:0] = decimal point
- */
- uint16_t length;
- uint8_t enable;
- uint8_t oc_pin;
- uint8_t location;
-} __attribute__((packed));
-
-struct usb3_port_setting {
- uint8_t enable;
- uint8_t oc_pin;
- /*
- * Set to 0 if trace length is > 5 inches
- * Set to 1 if trace length is <= 5 inches
- */
- uint8_t fixed_eq;
-} __attribute__((packed));
-
-struct pei_data
-{
- uint32_t pei_version;
-
- enum board_type board_type;
- int boot_mode;
- int ec_present;
- int usbdebug;
-
- /* Base addresses */
- uint32_t pciexbar;
- uint16_t smbusbar;
- uint32_t xhcibar;
- uint32_t ehcibar;
- uint32_t gttbar;
- uint32_t rcba;
- uint32_t pmbase;
- uint32_t gpiobase;
- uint32_t temp_mmio_base;
- uint32_t tseg_size;
-
- /*
- * 0 = leave channel enabled
- * 1 = disable dimm 0 on channel
- * 2 = disable dimm 1 on channel
- * 3 = disable dimm 0+1 on channel
- */
- int dimm_channel0_disabled;
- int dimm_channel1_disabled;
- /* Set to 0 for memory down */
- uint8_t spd_addresses[4];
- /* Enable 2x Refresh Mode */
- int ddr_refresh_2x;
- /* DQ pins are interleaved on board */
- int dq_pins_interleaved;
- /* Limit DDR3 frequency */
- int max_ddr3_freq;
- /* Disable self refresh */
- int disable_self_refresh;
- /* Disable cmd power/CKEPD */
- int disable_cmd_pwr;
-
- /* USB port configuration */
- struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
- struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
-
- /*
- * USB3 board specific PHY tuning
- */
-
- /* Valid range: 0x69 - 0x80 */
- uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
- /* Valid range: 0x80 - 0x9c */
- uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
- /* Valid range: 0x39 - 0x80 */
- uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
- /* Valid range: 0x3d - 0x4a */
- uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
-
- /* Console output function */
- tx_byte_func tx_byte;
-
- /*
- * DIMM SPD data for memory down configurations
- * [CHANNEL][SLOT][SPD]
- */
- uint8_t spd_data[2][2][512];
-
- /*
- * LPDDR3 DQ byte map
- * [CHANNEL][ITERATION][2]
- *
- * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
- * DQByteMap[0] - ClkDQByteMap:
- * - If clock is per rank, program to [0xFF, 0xFF]
- * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
- * - If clock is shared by 2 ranks but does not go to all bytes,
- * Entry[i] defines which DQ bytes Group i services
- * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
- * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
- * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
- * For DDR, DQByteMap[3:1] = [0xFF, 0]
- * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
- * since we have 1 CTL / rank
- * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
- * since we have 1 CA Vref
- */
- uint8_t dq_map[2][6][2];
-
- /*
- * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
- * [CHANNEL][MAX_BYTES]
- */
- uint8_t dqs_map[2][8];
-
- /* Data read from flash and passed into MRC */
- const void *saved_data;
- int saved_data_size;
-
- /* Disable use of saved data (can be set by mainboard) */
- int disable_saved_data;
-
- /* Data from MRC that should be saved to flash */
- void *data_to_save;
- int data_to_save_size;
- struct memory_info meminfo;
-} __attribute__((packed));
-
-typedef struct pei_data PEI_DATA;
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/pei_wrapper.h b/src/soc/intel/broadwell/broadwell/pei_wrapper.h
deleted file mode 100644
index 9791fa5..0000000
--- a/src/soc/intel/broadwell/broadwell/pei_wrapper.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_PEI_WRAPPER_H_
-#define _BROADWELL_PEI_WRAPPER_H_
-
-#include <broadwell/pei_data.h>
-
-typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
-
-static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
- uint16_t length, uint8_t enable,
- uint8_t oc_pin, uint8_t location)
-{
- pei_data->usb2_ports[port].length = length;
- pei_data->usb2_ports[port].enable = enable;
- pei_data->usb2_ports[port].oc_pin = oc_pin;
- pei_data->usb2_ports[port].location = location;
-}
-
-static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
- uint8_t enable, uint8_t oc_pin,
- uint8_t fixed_eq)
-{
- pei_data->usb3_ports[port].enable = enable;
- pei_data->usb3_ports[port].oc_pin = oc_pin;
- pei_data->usb3_ports[port].fixed_eq = fixed_eq;
-}
-
-void broadwell_fill_pei_data(struct pei_data *pei_data);
-void mainboard_fill_pei_data(struct pei_data *pei_data);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/pm.h b/src/soc/intel/broadwell/broadwell/pm.h
deleted file mode 100644
index 6bc98ef..0000000
--- a/src/soc/intel/broadwell/broadwell/pm.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_PM_H_
-#define _BROADWELL_PM_H_
-
-/* ACPI_BASE_ADDRESS / PMBASE */
-
-#define PM1_STS 0x00
-#define WAK_STS (1 << 15)
-#define PCIEXPWAK_STS (1 << 14)
-#define PRBTNOR_STS (1 << 11)
-#define RTC_STS (1 << 10)
-#define PWRBTN_STS (1 << 8)
-#define GBL_STS (1 << 5)
-#define BM_STS (1 << 4)
-#define TMROF_STS (1 << 0)
-#define PM1_EN 0x02
-#define PCIEXPWAK_DIS (1 << 14)
-#define RTC_EN (1 << 10)
-#define PWRBTN_EN (1 << 8)
-#define GBL_EN (1 << 5)
-#define TMROF_EN (1 << 0)
-#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define SLP_TYP_SHIFT 10
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
-#define GBL_RLS (1 << 2)
-#define BM_RLD (1 << 1)
-#define SCI_EN (1 << 0)
-#define PM1_TMR 0x08
-#define SMI_EN 0x30
-#define XHCI_SMI_EN (1 << 31)
-#define ME_SMI_EN (1 << 30)
-#define GPIO_UNLOCK_SMI_EN (1 << 27)
-#define INTEL_USB2_EN (1 << 18)
-#define LEGACY_USB2_EN (1 << 17)
-#define PERIODIC_EN (1 << 14)
-#define TCO_EN (1 << 13)
-#define MCSMI_EN (1 << 11)
-#define BIOS_RLS (1 << 7)
-#define SWSMI_TMR_EN (1 << 6)
-#define APMC_EN (1 << 5)
-#define SLP_SMI_EN (1 << 4)
-#define LEGACY_USB_EN (1 << 3)
-#define BIOS_EN (1 << 2)
-#define EOS (1 << 1)
-#define GBL_SMI_EN (1 << 0)
-#define SMI_STS 0x34
-#define UPWRC 0x3c
-#define UPWRC_WS (1 << 8)
-#define UPWRC_WE (1 << 1)
-#define UPWRC_SMI (1 << 0)
-#define GPE_CNTL 0x42
-#define SWGPE_CTRL (1 << 1)
-#define DEVACT_STS 0x44
-#define PM2_CNT 0x50
-#define TCO1_CNT 0x60
-#define TCO_TMR_HLT (1 << 11)
-#define TCO1_STS 0x64
-#define DMISCI_STS (1 << 9)
-#define TCO2_STS 0x66
-#define TCO2_STS_SECOND_TO (1 << 1)
-
-#define GPE0_STS(x) (0x80 + (x * 4))
-#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
-#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
-#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
-#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
-#define WADT_STS (1 << 18)
-#define GP27_STS (1 << 16)
-#define PME_B0_STS (1 << 13)
-#define ME_SCI_STS (1 << 12)
-#define PME_STS (1 << 11)
-#define BATLOW_STS (1 << 10)
-#define PCI_EXP_STS (1 << 9)
-#define SMB_WAK_STS (1 << 7)
-#define TCOSCI_STS (1 << 6)
-#define SWGPE_STS (1 << 2)
-#define HOT_PLUG_STS (1 << 1)
-#define GPE0_EN(x) (0x90 + (x * 4))
-#define WADT_en (1 << 18)
-#define GP27_EN (1 << 16)
-#define PME_B0_EN (1 << 13)
-#define ME_SCI_EN (1 << 12)
-#define PME_EN (1 << 11)
-#define BATLOW_EN (1 << 10)
-#define PCI_EXP_EN (1 << 9)
-#define TCOSCI_EN (1 << 6)
-#define SWGPE_EN (1 << 2)
-#define HOT_PLUG_EN (1 << 1)
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-#define MAINBOARD_POWER_KEEP 2
-
-#define SLEEP_STATE_S0 0
-#define SLEEP_STATE_S3 3
-#define SLEEP_STATE_S5 5
-
-struct chipset_power_state {
- uint16_t pm1_sts;
- uint16_t pm1_en;
- uint32_t pm1_cnt;
- uint16_t tco1_sts;
- uint16_t tco2_sts;
- uint32_t gpe0_sts[4];
- uint32_t gpe0_en[4];
- uint16_t gen_pmcon1;
- uint16_t gen_pmcon2;
- uint16_t gen_pmcon3;
- int prev_sleep_state;
- uint16_t hsio_version;
- uint16_t hsio_checksum;
-};
-
-/* PM1_CNT */
-void enable_pm1_control(uint32_t mask);
-void disable_pm1_control(uint32_t mask);
-
-/* PM1 */
-uint16_t clear_pm1_status(void);
-void enable_pm1(uint16_t events);
-uint32_t clear_smi_status(void);
-
-/* SMI */
-void enable_smi(uint32_t mask);
-void disable_smi(uint32_t mask);
-
-/* ALT_GP_SMI */
-uint32_t clear_alt_smi_status(void);
-void enable_alt_smi(uint32_t mask);
-
-/* TCO */
-uint32_t clear_tco_status(void);
-void enable_tco_sci(void);
-
-/* GPE0 */
-uint32_t clear_gpe_status(void);
-void clear_gpe_enable(void);
-void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4);
-void disable_all_gpe(void);
-void enable_gpe(uint32_t mask);
-void disable_gpe(uint32_t mask);
-
-/* Return the selected ACPI SCI IRQ */
-int acpi_sci_irq(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h
deleted file mode 100644
index 685de14..0000000
--- a/src/soc/intel/broadwell/broadwell/ramstage.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_RAMSTAGE_H_
-#define _BROADWELL_RAMSTAGE_H_
-
-#include <device/device.h>
-#include <chip.h>
-
-void broadwell_init_pre_device(void *chip_info);
-void broadwell_init_cpus(device_t dev);
-void broadwell_pch_enable_dev(device_t dev);
-
-#if CONFIG_HAVE_REFCODE_BLOB
-void broadwell_run_reference_code(void);
-#else
-static inline void broadwell_run_reference_code(void) { }
-#endif
-
-extern struct pci_operations broadwell_pci_ops;
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/rcba.h b/src/soc/intel/broadwell/broadwell/rcba.h
deleted file mode 100644
index c550c2d..0000000
--- a/src/soc/intel/broadwell/broadwell/rcba.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_RCBA_H_
-#define _BROADWELL_RCBA_H_
-
-#include <broadwell/iomap.h>
-
-#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x))
-#define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x))
-#define RCBA32(x) *((volatile u32 *)(RCBA_BASE_ADDRESS + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
-#define RPC 0x0400 /* 32bit */
-#define RPFN 0x0404 /* 32bit */
-
-/* Root Port configuration space hide */
-#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
-/* Get the function number assigned to a Root Port */
-#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
-/* Set the function number for a Root Port */
-#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
-/* Root Port function number mask */
-#define RPFN_FNMASK(port) (7 << ((port) * 4))
-
-#define NOINT 0
-#define INTA 1
-#define INTB 2
-#define INTC 3
-#define INTD 4
-
-#define DIR_IDR 12 /* Interrupt D Pin Offset */
-#define DIR_ICR 8 /* Interrupt C Pin Offset */
-#define DIR_IBR 4 /* Interrupt B Pin Offset */
-#define DIR_IAR 0 /* Interrupt A Pin Offset */
-
-#define PIRQA 0
-#define PIRQB 1
-#define PIRQC 2
-#define PIRQD 3
-#define PIRQE 4
-#define PIRQF 5
-#define PIRQG 6
-#define PIRQH 7
-
-/* IO Buffer Programming */
-#define IOBPIRI 0x2330
-#define IOBPD 0x2334
-#define IOBPS 0x2338
-#define IOBPS_READY 0x0001
-#define IOBPS_TX_MASK 0x0006
-#define IOBPS_MASK 0xff00
-#define IOBPS_READ 0x0600
-#define IOBPS_WRITE 0x0700
-#define IOBPU 0x233a
-#define IOBPU_MAGIC 0xf000
-#define IOBP_PCICFG_READ 0x0400
-#define IOBP_PCICFG_WRITE 0x0500
-
-#define D31IP 0x3100 /* 32bit */
-#define D31IP_TTIP 24 /* Thermal Throttle Pin */
-#define D31IP_SIP2 20 /* SATA Pin 2 */
-#define D31IP_SMIP 12 /* SMBUS Pin */
-#define D31IP_SIP 8 /* SATA Pin */
-#define D30IP 0x3104 /* 32bit */
-#define D30IP_PIP 0 /* PCI Bridge Pin */
-#define D29IP 0x3108 /* 32bit */
-#define D29IP_E1P 0 /* EHCI #1 Pin */
-#define D28IP 0x310c /* 32bit */
-#define D28IP_P8IP 28 /* PCI Express Port 8 */
-#define D28IP_P7IP 24 /* PCI Express Port 7 */
-#define D28IP_P6IP 20 /* PCI Express Port 6 */
-#define D28IP_P5IP 16 /* PCI Express Port 5 */
-#define D28IP_P4IP 12 /* PCI Express Port 4 */
-#define D28IP_P3IP 8 /* PCI Express Port 3 */
-#define D28IP_P2IP 4 /* PCI Express Port 2 */
-#define D28IP_P1IP 0 /* PCI Express Port 1 */
-#define D27IP 0x3110 /* 32bit */
-#define D27IP_ZIP 0 /* HD Audio Pin */
-#define D26IP 0x3114 /* 32bit */
-#define D26IP_E2P 0 /* EHCI #2 Pin */
-#define D25IP 0x3118 /* 32bit */
-#define D25IP_LIP 0 /* GbE LAN Pin */
-#define D22IP 0x3124 /* 32bit */
-#define D22IP_KTIP 12 /* KT Pin */
-#define D22IP_IDERIP 8 /* IDE-R Pin */
-#define D22IP_MEI2IP 4 /* MEI #2 Pin */
-#define D22IP_MEI1IP 0 /* MEI #1 Pin */
-#define D20IP 0x3128 /* 32bit */
-#define D20IP_XHCI 0 /* XHCI Pin */
-#define D31IR 0x3140 /* 16bit */
-#define D30IR 0x3142 /* 16bit */
-#define D29IR 0x3144 /* 16bit */
-#define D28IR 0x3146 /* 16bit */
-#define D27IR 0x3148 /* 16bit */
-#define D26IR 0x314c /* 16bit */
-#define D25IR 0x3150 /* 16bit */
-#define D23IR 0x3158 /* 16bit */
-#define D22IR 0x315c /* 16bit */
-#define D20IR 0x3160 /* 16bit */
-#define D21IR 0x3164 /* 16bit */
-#define D19IR 0x3168 /* 16bit */
-#define ACPIIRQEN 0x31e0 /* 32bit */
-#define OIC 0x31fe /* 16bit */
-#define DEEP_S3_POL 0x3328 /* 32bit */
-#define DEEP_S3_EN_AC (1 << 0)
-#define DEEP_S3_EN_DC (1 << 1)
-#define DEEP_S5_POL 0x3330 /* 32bit */
-#define DEEP_S5_EN_AC (1 << 14)
-#define DEEP_S5_EN_DC (1 << 15)
-#define DEEP_SX_CONFIG 0x3334 /* 32bit */
-#define DEEP_SX_WAKE_PIN_EN (1 << 2)
-#define DEEP_SX_ACPRESENT_PD (1 << 1)
-#define DEEP_SX_GP27_PIN_EN (1 << 0)
-#define PMSYNC_CONFIG 0x33c4 /* 32bit */
-#define PMSYNC_CONFIG2 0x33cc /* 32bit */
-#define SOFT_RESET_CTRL 0x38f4
-#define SOFT_RESET_DATA 0x38f8
-
-#define DIR_ROUTE(a,b,c,d) \
- (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
-
-#define RC 0x3400 /* 32bit */
-#define HPTC 0x3404 /* 32bit */
-#define GCS 0x3410 /* 32bit */
-#define BUC 0x3414 /* 32bit */
-#define PCH_DISABLE_GBE (1 << 5)
-#define FD 0x3418 /* 32bit */
-#define FDSW 0x3420 /* 8bit */
-#define DISPBDF 0x3424 /* 16bit */
-#define FD2 0x3428 /* 32bit */
-#define CG 0x341c /* 32bit */
-
-/* Function Disable 1 RCBA 0x3418 */
-#define PCH_DISABLE_ALWAYS (1 << 0)
-#define PCH_DISABLE_ADSPD (1 << 1)
-#define PCH_DISABLE_SATA1 (1 << 2)
-#define PCH_DISABLE_SMBUS (1 << 3)
-#define PCH_DISABLE_HD_AUDIO (1 << 4)
-#define PCH_DISABLE_EHCI2 (1 << 13)
-#define PCH_DISABLE_LPC (1 << 14)
-#define PCH_DISABLE_EHCI1 (1 << 15)
-#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
-#define PCH_DISABLE_THERMAL (1 << 24)
-#define PCH_DISABLE_SATA2 (1 << 25)
-#define PCH_DISABLE_XHCI (1 << 27)
-
-/* Function Disable 2 RCBA 0x3428 */
-#define PCH_DISABLE_KT (1 << 4)
-#define PCH_DISABLE_IDER (1 << 3)
-#define PCH_DISABLE_MEI2 (1 << 2)
-#define PCH_DISABLE_MEI1 (1 << 1)
-#define PCH_ENABLE_DBDF (1 << 0)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/reset.h b/src/soc/intel/broadwell/broadwell/reset.h
deleted file mode 100644
index 6f21181..0000000
--- a/src/soc/intel/broadwell/broadwell/reset.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_RESET_H_
-#define _BROADWELL_RESET_H_
-
-void reset_system(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/romstage.h b/src/soc/intel/broadwell/broadwell/romstage.h
deleted file mode 100644
index 946d1d0..0000000
--- a/src/soc/intel/broadwell/broadwell/romstage.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_ROMSTAGE_H_
-#define _BROADWELL_ROMSTAGE_H_
-
-#include <stdint.h>
-#include <arch/cpu.h>
-
-struct chipset_power_state;
-struct pei_data;
-struct romstage_params {
- unsigned long bist;
- struct chipset_power_state *power_state;
- struct pei_data *pei_data;
-};
-
-void mainboard_romstage_entry(struct romstage_params *params);
-void romstage_common(struct romstage_params *params);
-void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
- uint32_t tsc_high);
-void asmlinkage romstage_after_car(void);
-void raminit(struct pei_data *pei_data);
-void *setup_stack_and_mttrs(void);
-
-struct chipset_power_state;
-struct chipset_power_state *fill_power_state(void);
-void report_platform_info(void);
-void report_memory_config(void);
-
-void set_max_freq(void);
-
-void systemagent_early_init(void);
-void pch_early_init(void);
-void pch_uart_init(void);
-void intel_early_me_status(void);
-
-void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
-
-int early_spi_read(u32 offset, u32 size, u8 *buffer);
-int early_spi_read_wpsr(u8 *sr);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/sata.h b/src/soc/intel/broadwell/broadwell/sata.h
deleted file mode 100644
index 357fe58..0000000
--- a/src/soc/intel/broadwell/broadwell/sata.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_SATA_H_
-#define _BROADWELL_SATA_H_
-
-#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
-#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
-#define SATA_SP 0xd0 /* Scratchpad */
-
-/* SATA IOBP Registers */
-#define SATA_IOBP_SP0G3IR 0xea000151
-#define SATA_IOBP_SP1G3IR 0xea000051
-#define SATA_IOBP_SP0DTLE_DATA 0xea002550
-#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
-#define SATA_IOBP_SP1DTLE_DATA 0xea002750
-#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
-
-#define SATA_DTLE_MASK 0xF
-#define SATA_DTLE_DATA_SHIFT 24
-#define SATA_DTLE_EDGE_SHIFT 16
-
-/* PCI Configuration Space (D31:F1): IDE */
-#define INTR_LN 0x3c
-#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
-#define IDE_DECODE_ENABLE (1 << 15)
-#define IDE_SITRE (1 << 14)
-#define IDE_ISP_5_CLOCKS (0 << 12)
-#define IDE_ISP_4_CLOCKS (1 << 12)
-#define IDE_ISP_3_CLOCKS (2 << 12)
-#define IDE_RCT_4_CLOCKS (0 << 8)
-#define IDE_RCT_3_CLOCKS (1 << 8)
-#define IDE_RCT_2_CLOCKS (2 << 8)
-#define IDE_RCT_1_CLOCKS (3 << 8)
-#define IDE_DTE1 (1 << 7)
-#define IDE_PPE1 (1 << 6)
-#define IDE_IE1 (1 << 5)
-#define IDE_TIME1 (1 << 4)
-#define IDE_DTE0 (1 << 3)
-#define IDE_PPE0 (1 << 2)
-#define IDE_IE0 (1 << 1)
-#define IDE_TIME0 (1 << 0)
-#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
-
-#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
-#define IDE_SSDE1 (1 << 3)
-#define IDE_SSDE0 (1 << 2)
-#define IDE_PSDE1 (1 << 1)
-#define IDE_PSDE0 (1 << 0)
-
-#define IDE_SDMA_TIM 0x4a
-
-#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
-#define SIG_MODE_SEC_NORMAL (0 << 18)
-#define SIG_MODE_SEC_TRISTATE (1 << 18)
-#define SIG_MODE_SEC_DRIVELOW (2 << 18)
-#define SIG_MODE_PRI_NORMAL (0 << 16)
-#define SIG_MODE_PRI_TRISTATE (1 << 16)
-#define SIG_MODE_PRI_DRIVELOW (2 << 16)
-#define FAST_SCB1 (1 << 15)
-#define FAST_SCB0 (1 << 14)
-#define FAST_PCB1 (1 << 13)
-#define FAST_PCB0 (1 << 12)
-#define SCB1 (1 << 3)
-#define SCB0 (1 << 2)
-#define PCB1 (1 << 1)
-#define PCB0 (1 << 0)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/serialio.h b/src/soc/intel/broadwell/broadwell/serialio.h
deleted file mode 100644
index 2fd6dca..0000000
--- a/src/soc/intel/broadwell/broadwell/serialio.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_SERIALIO_H_
-#define _BROADWELL_SERIALIO_H_
-
-/* Serial IO IOBP Registers */
-#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
-#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
-#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
-#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
-#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
-#define SIO_IOBP_GPIODF 0xcb000154
-#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
-#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
-#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
-#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
-#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
-#define SIO_IOBP_GPIODF_UART0_BYTE_ACCESS (1 << 10)
-#define SIO_IOBP_GPIODF_UART1_BYTE_ACCESS (1 << 11)
-#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
-#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
-#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
-#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */
-#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */
-#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */
-#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
-#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
-/* PORTCTRL 2-8 have the same layout */
-#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
-#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
-#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
-#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
-#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
-#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
-#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
-#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
-#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */
-#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */
-#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
-#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
-#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
-#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
-
-/* Serial IO Devices */
-#define SIO_ID_SDMA 0 /* D21:F0 */
-#define SIO_ID_I2C0 1 /* D21:F1 */
-#define SIO_ID_I2C1 2 /* D21:F2 */
-#define SIO_ID_SPI0 3 /* D21:F3 */
-#define SIO_ID_SPI1 4 /* D21:F4 */
-#define SIO_ID_UART0 5 /* D21:F5 */
-#define SIO_ID_UART1 6 /* D21:F6 */
-#define SIO_ID_SDIO 7 /* D23:F0 */
-
-#define SIO_REG_PPR_CLOCK 0x800
-#define SIO_REG_PPR_CLOCK_EN (1 << 0)
-#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31)
-#define SIO_REG_PPR_CLOCK_M_DIV 0x25a
-#define SIO_REG_PPR_CLOCK_N_DIV 0x7fff
-#define SIO_REG_PPR_RST 0x804
-#define SIO_REG_PPR_RST_ASSERT 0x3
-#define SIO_REG_PPR_GEN 0x808
-#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
-#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
-#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
-#define SIO_REG_AUTO_LTR 0x814
-
-#define SIO_REG_SDIO_PPR_GEN 0x1008
-#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
-#define SIO_REG_SDIO_PPR_CMD12 0x3c
-#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
-
-#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
-#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
-#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
-#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/smbus.h b/src/soc/intel/broadwell/broadwell/smbus.h
deleted file mode 100644
index fb13c2d..0000000
--- a/src/soc/intel/broadwell/broadwell/smbus.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
- * Copyright (C) 2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_SMBUS_H_
-#define _BROADWELL_SMBUS_H_
-
-/* PCI Configuration Space (D31:F3): SMBus */
-#define SMB_BASE 0x20
-#define HOSTC 0x40
-#define HST_EN (1 << 0)
-#define SMB_RCV_SLVA 0x09
-
-/* SMBus I/O bits. */
-#define SMBHSTSTAT 0x0
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-#define SMBUS_TIMEOUT (10 * 1000 * 100)
-#define SMBUS_SLAVE_ADDR 0x24
-
-int do_smbus_read_byte(unsigned smbus_base, unsigned device,
- unsigned address);
-int do_smbus_write_byte(unsigned smbus_base, unsigned device,
- unsigned address, unsigned data);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/smm.h b/src/soc/intel/broadwell/broadwell/smm.h
deleted file mode 100644
index f7f515c..0000000
--- a/src/soc/intel/broadwell/broadwell/smm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_SMM_H_
-#define _BROADWELL_SMM_H_
-
-#include <stdint.h>
-#include <cpu/x86/msr.h>
-
-struct ied_header {
- char signature[10];
- u32 size;
- u8 reserved[34];
-} __attribute__ ((packed));
-
-struct smm_relocation_params {
- u32 smram_base;
- u32 smram_size;
- u32 ied_base;
- u32 ied_size;
- msr_t smrr_base;
- msr_t smrr_mask;
- msr_t emrr_base;
- msr_t emrr_mask;
- msr_t uncore_emrr_base;
- msr_t uncore_emrr_mask;
- /* The smm_save_state_in_msrs field indicates if SMM save state
- * locations live in MSRs. This indicates to the CPUs how to adjust
- * the SMMBASE and IEDBASE */
- int smm_save_state_in_msrs;
-};
-
-/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
- * is included after chipset code. This causes the chipset's Kconfig to be
- * clobbered by the arch/x86/Kconfig if they have the same name. */
-static inline int smm_region_size(void)
-{
- /* Make it 8MiB by default. */
- if (CONFIG_SMM_TSEG_SIZE == 0)
- return (8 << 20);
- return CONFIG_SMM_TSEG_SIZE;
-}
-
-int smm_initialize(void);
-void smm_relocate(void);
-
-/* These helpers are for performing SMM relocation. */
-void southbridge_trigger_smi(void);
-void southbridge_clear_smi_status(void);
-
-/* The initialization of the southbridge is split into 2 components. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions. */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/spi.h b/src/soc/intel/broadwell/broadwell/spi.h
deleted file mode 100644
index 8b95f70..0000000
--- a/src/soc/intel/broadwell/broadwell/spi.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_SPI_H_
-#define _BROADWELL_SPI_H_
-
-/*
- * SPI Opcode Menu setup for SPIBAR lockdown
- * should support most common flash chips.
- */
-
-#define SPIBAR_OFFSET 0x3800
-#define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET)
-#define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET)
-#define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET)
-
-/* Registers within the SPIBAR */
-#define SPIBAR_SSFC 0x91
-#define SPIBAR_FDOC 0xb0
-#define SPIBAR_FDOD 0xb4
-
-#define SPIBAR_PREOP 0x94
-#define SPIBAR_OPTYPE 0x96
-#define SPIBAR_OPMENU_LOWER 0x98
-#define SPIBAR_OPMENU_UPPER 0x9c
-
-#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
-#define SPI_OPTYPE_0 0x01 /* Write, no address */
-
-#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
-#define SPI_OPTYPE_1 0x03 /* Write, address required */
-
-#define SPI_OPMENU_2 0x03 /* READ: Read Data */
-#define SPI_OPTYPE_2 0x02 /* Read, address required */
-
-#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
-#define SPI_OPTYPE_3 0x00 /* Read, no address */
-
-#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
-#define SPI_OPTYPE_4 0x03 /* Write, address required */
-
-#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
-#define SPI_OPTYPE_5 0x00 /* Read, no address */
-
-#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
-#define SPI_OPTYPE_6 0x03 /* Write, address required */
-
-#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
-#define SPI_OPTYPE_7 0x02 /* Read, address required */
-
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
- (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
- (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
-
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
- (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
- (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
- (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
-
-#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-
-#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
-#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
-#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
-#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
-#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
-#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
-#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
-#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
-#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
-#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
-#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
-#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
-#define SPIBAR_FADDR 0x08 /* SPI flash address */
-#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
-#define SPIBAR_SSFS 0x90
-#define SPIBAR_SSFS_ERROR (1 << 3)
-#define SPIBAR_SSFS_DONE (1 << 2)
-#define SPIBAR_SSFC 0x91
-#define SPIBAR_SSFC_DATA (1 << 14)
-#define SPIBAR_SSFC_GO (1 << 1)
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h
deleted file mode 100644
index 61ea56a..0000000
--- a/src/soc/intel/broadwell/broadwell/systemagent.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_SYSTEMAGENT_H_
-#define _BROADWELL_SYSTEMAGENT_H_
-
-#include <broadwell/iomap.h>
-
-#define SA_IGD_OPROM_VENDEV 0x80860406
-
-#define IGD_HASWELL_ULT_GT1 0x0a06
-#define IGD_HASWELL_ULT_GT2 0x0a16
-#define IGD_HASWELL_ULT_GT3 0x0a26
-#define IGD_BROADWELL_U_GT1 0x1606
-#define IGD_BROADWELL_U_GT2 0x1616
-#define IGD_BROADWELL_U_GT3_15W 0x1626
-#define IGD_BROADWELL_U_GT3_28W 0x162b
-#define IGD_BROADWELL_Y_GT2 0x161e
-#define IGD_BROADWELL_H_GT2 0x1612
-#define IGD_BROADWELL_H_GT3 0x1622
-
-#define MCH_BROADWELL_ID_U_Y 0x1604
-#define MCH_BROADWELL_REV_D0 0x06
-#define MCH_BROADWELL_REV_E0 0x08
-#define MCH_BROADWELL_REV_F0 0x09
-
-/* Device 0:0.0 PCI configuration space */
-
-#define EPBAR 0x40
-#define MCHBAR 0x48
-#define PCIEXBAR 0x60
-#define DMIBAR 0x68
-#define GGC 0x50 /* GMCH Graphics Control */
-#define DEVEN 0x54 /* Device Enable */
-#define DEVEN_D7EN (1 << 14)
-#define DEVEN_D4EN (1 << 7)
-#define DEVEN_D3EN (1 << 5)
-#define DEVEN_D2EN (1 << 4)
-#define DEVEN_D1F0EN (1 << 3)
-#define DEVEN_D1F1EN (1 << 2)
-#define DEVEN_D1F2EN (1 << 1)
-#define DEVEN_D0EN (1 << 0)
-#define DPR 0x5c
-#define DPR_EPM (1 << 2)
-#define DPR_PRS (1 << 1)
-#define DPR_SIZE_MASK 0xff0
-
-#define PAM0 0x80
-#define PAM1 0x81
-#define PAM2 0x82
-#define PAM3 0x83
-#define PAM4 0x84
-#define PAM5 0x85
-#define PAM6 0x86
-
-#define SMRAM 0x88 /* System Management RAM Control */
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-
-#define MESEG_BASE 0x70 /* Management Engine Base. */
-#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
-#define REMAPBASE 0x90 /* Remap base. */
-#define REMAPLIMIT 0x98 /* Remap limit. */
-#define TOM 0xa0 /* Top of DRAM in memory controller space. */
-#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
-#define BDSM 0xb0 /* Base Data Stolen Memory */
-#define BGSM 0xb4 /* Base GTT Stolen Memory */
-#define TSEG 0xb8 /* TSEG base */
-#define TOLUD 0xbc /* Top of Low Used Memory */
-#define SKPAD 0xdc /* Scratchpad Data */
-
-/* MCHBAR */
-
-#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x))
-#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x))
-#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x))
-
-#define MCHBAR_PEI_VERSION 0x5034
-#define BIOS_RESET_CPL 0x5da8
-#define EDRAMBAR 0x5408
-#define MCH_PAIR 0x5418
-#define GDXCBAR 0x5420
-
-#define MCH_PKG_POWER_LIMIT_LO 0x59a0
-#define MCH_PKG_POWER_LIMIT_HI 0x59a4
-#define MCH_DDR_POWER_LIMIT_LO 0x58e0
-#define MCH_DDR_POWER_LIMIT_HI 0x58e4
-
-/* PCODE MMIO communications live in the MCHBAR. */
-#define BIOS_MAILBOX_INTERFACE 0x5da4
-#define MAILBOX_RUN_BUSY (1 << 31)
-#define MAILBOX_BIOS_CMD_READ_PCS 1
-#define MAILBOX_BIOS_CMD_WRITE_PCS 2
-#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
-#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
-#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
-#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
-/* Errors are returned back in bits 7:0. */
-#define MAILBOX_BIOS_ERROR_NONE 0
-#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
-#define MAILBOX_BIOS_ERROR_TIMEOUT 2
-#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
-#define MAILBOX_BIOS_ERROR_RESERVED 4
-#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
-#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
-#define MAILBOX_BIOS_ERROR_VR_ERROR 7
-/* Data is passed through bits 31:0 of the data register. */
-#define BIOS_MAILBOX_DATA 0x5da0
-
-/* System Agent identification */
-u8 systemagent_revision(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h
deleted file mode 100644
index 3f4fb4e..0000000
--- a/src/soc/intel/broadwell/broadwell/xhci.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _BROADWELL_XHCI_H_
-#define _BROADWELL_XHCI_H_
-
-/* XHCI PCI Registers */
-#define XHCI_PWR_CTL_STS 0x74
-#define XHCI_PWR_CTL_SET_MASK 0x3
-#define XHCI_PWR_CTL_SET_D0 0x0
-#define XHCI_PWR_CTL_SET_D3 0x3
-#define XHCI_PWR_CTL_ENABLE_PME (1 << 8)
-#define XHCI_PWR_CTL_STATUS_PME (1 << 15)
-#define XHCI_USB2PR 0xd0
-#define XHCI_USB2PRM 0xd4
-#define XHCI_USB2PR_HCSEL 0x7fff
-#define XHCI_USB3PR 0xd8
-#define XHCI_USB3PR_SSEN 0x3f
-#define XHCI_USB3PRM 0xdc
-#define XHCI_USB3FUS 0xe0
-#define XHCI_USB3FUS_SS_MASK 3
-#define XHCI_USB3FUS_SS_SHIFT 3
-#define XHCI_USB3PDO 0xe8
-
-/* XHCI Memory Registers */
-#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
-#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
-#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
-#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
-#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
-#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
-#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
-#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
-#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
-#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
-#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
-#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
-#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
-#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
-
-#ifdef __SMM__
-void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
-#endif
-
-#endif
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index eecb0cf..0026152 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -20,9 +20,9 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <chip.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/intel/broadwell/chip.h>
static void pci_domain_set_resources(device_t dev)
{
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 912f8ae..b227e0d 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -36,14 +36,14 @@
#include <cpu/x86/smm.h>
#include <delay.h>
#include <pc80/mc146818rtc.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/smm.h>
-#include <broadwell/systemagent.h>
-#include <chip.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
+#include <soc/intel/broadwell/chip.h>
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c
index a13ca94..72667ac 100644
--- a/src/soc/intel/broadwell/cpu_info.c
+++ b/src/soc/intel/broadwell/cpu_info.c
@@ -21,9 +21,9 @@
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/systemagent.h>
u32 cpu_family_model(void)
{
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index 2b8a9be..3073a54 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -24,8 +24,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
-#include <broadwell/ehci.h>
-#include <broadwell/pch.h>
+#include <soc/ehci.h>
+#include <soc/pch.h>
static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c
index 30f64e0..8cbc3e7 100644
--- a/src/soc/intel/broadwell/elog.c
+++ b/src/soc/intel/broadwell/elog.c
@@ -22,8 +22,8 @@
#include <console/console.h>
#include <stdint.h>
#include <elog.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pm.h>
+#include <soc/lpc.h>
+#include <soc/pm.h>
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
{
diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index bf77a87..b4c2031 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -25,12 +25,12 @@
#include <reg_script.h>
#include <spi-generic.h>
#include <stdlib.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/lpc.h>
-#include <broadwell/me.h>
-#include <broadwell/rcba.h>
-#include <broadwell/spi.h>
-#include <broadwell/systemagent.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
+#include <soc/me.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
+#include <soc/systemagent.h>
const struct reg_script system_agent_finalize_script[] = {
REG_PCI_OR16(0x50, 1 << 0), /* GGC */
diff --git a/src/soc/intel/broadwell/gpio.c b/src/soc/intel/broadwell/gpio.c
index 92699d2..dc7d713 100644
--- a/src/soc/intel/broadwell/gpio.c
+++ b/src/soc/intel/broadwell/gpio.c
@@ -22,9 +22,9 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
/*
* This function will return a number that indicates which PIRQ
diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c
index ba648db..b2992e8 100644
--- a/src/soc/intel/broadwell/hda.c
+++ b/src/soc/intel/broadwell/hda.c
@@ -27,9 +27,9 @@
#include <arch/io.h>
#include <delay.h>
#include <soc/intel/common/hda_verb.h>
-#include <broadwell/pch.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
+#include <soc/pch.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
const u32 * cim_verb_data = NULL;
u32 cim_verb_data_size = 0;
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 53d108d..714a139 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -28,10 +28,10 @@
#include <string.h>
#include <reg_script.h>
#include <drivers/intel/gma/i915_reg.h>
-#include <broadwell/cpu.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/systemagent.h>
-#include <chip.h>
+#include <soc/cpu.h>
+#include <soc/ramstage.h>
+#include <soc/systemagent.h>
+#include <soc/intel/broadwell/chip.h>
#define GT_RETRY 1000
#define GT_CDCLK_337 0
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h
new file mode 100644
index 0000000..2b1e77e
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/acpi.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_ACPI_H_
+#define _BROADWELL_ACPI_H_
+
+#include <arch/acpi.h>
+#include <soc/nvs.h>
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES 8
+#define PSS_RATIO_STEP 2
+#define PSS_LATENCY_TRANSITION 10
+#define PSS_LATENCY_BUSMASTER 10
+
+void acpi_create_intel_hpet(acpi_hpet_t *hpet);
+void acpi_fill_in_fadt(acpi_fadt_t *fadt);
+unsigned long acpi_madt_irq_overrides(unsigned long current);
+void acpi_init_gnvs(global_nvs_t *gnvs);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/adsp.h b/src/soc/intel/broadwell/include/soc/adsp.h
new file mode 100644
index 0000000..747a123
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/adsp.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_ADSP_H_
+#define _BROADWELL_ADSP_H_
+
+#define ADSP_PCI_IRQ 23
+#define ADSP_ACPI_IRQ 3
+#define ADSP_ACPI_IRQEN (1 << 3)
+
+#define ADSP_SHIM_BASE_LPT 0xe7000
+#define ADSP_SHIM_BASE_WPT 0xfb000
+#define ADSP_SHIM_LTRC 0xe0
+#define ADSP_SHIM_LTRC_VALUE 0x3003
+#define ADSP_SHIM_IMC 0x28
+#define ADSP_SHIM_IPCD 0x40
+
+#define ADSP_PCI_VDRTCTL0 0xa0
+#define ADSP_VDRTCTL0_D3PGD_LPT (1 << 1)
+#define ADSP_VDRTCTL0_D3PGD_WPT (1 << 0)
+#define ADSP_VDRTCTL0_D3SRAMPGD_LPT (1 << 2)
+#define ADSP_VDRTCTL0_D3SRAMPGD_WPT (1 << 1)
+#define ADSP_PCI_VDRTCTL1 0xa4
+#define ADSP_PCI_VDRTCTL2 0xa8
+#define ADSP_VDRTCTL2_VALUE 0x00000fff
+
+#define ADSP_IOBP_VDLDAT1 0xd7000624
+#define ADSP_VDLDAT1_VALUE 0x00040100
+#define ADSP_IOBP_VDLDAT2 0xd7000628
+#define ADSP_IOBP_ACPI_IRQ3 0xd9d8
+#define ADSP_IOBP_ACPI_IRQ3I 0xd8d9
+#define ADSP_IOBP_ACPI_IRQ4 0xdbda
+#define ADSP_IOBP_PMCTL 0xd70001e0
+#define ADSP_PMCTL_VALUE 0x3f
+#define ADSP_IOBP_PCICFGCTL 0xd7000500
+#define ADSP_PCICFGCTL_PCICD (1 << 0)
+#define ADSP_PCICFGCTL_ACPIIE (1 << 1)
+#define ADSP_PCICFGCTL_SPCBAD (1 << 7)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/cpu.h b/src/soc/intel/broadwell/include/soc/cpu.h
new file mode 100644
index 0000000..312532d
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/cpu.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_CPU_H_
+#define _BROADWELL_CPU_H_
+
+#include <arch/cpu.h>
+#include <device/device.h>
+
+/* CPU types */
+#define HASWELL_FAMILY_ULT 0x40650
+#define BROADWELL_FAMILY_ULT 0x306d0
+
+/* Supported CPUIDs */
+#define CPUID_HASWELL_A0 0x306c1
+#define CPUID_HASWELL_B0 0x306c2
+#define CPUID_HASWELL_C0 0x306c3
+#define CPUID_HASWELL_ULT_B0 0x40650
+#define CPUID_HASWELL_ULT 0x40651
+#define CPUID_HASWELL_HALO 0x40661
+#define CPUID_BROADWELL_C0 0x306d2
+#define CPUID_BROADWELL_D0 0x306d3
+#define CPUID_BROADWELL_E0 0x306d4
+
+/* CPU bus clock is fixed at 100MHz */
+#define CPU_BCLK 100
+
+/* Latency times in units of 1024ns. */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+
+#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
+ (((1 << ((base)*5)) * (limit)) / 1000)
+#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
+ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
+ (IRTL_1024_NS >> 10))
+
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+
+/*
+ * Determine if HyperThreading is disabled.
+ * The variable is not valid until setup_ap_init() has been called.
+ */
+extern int ht_disabled;
+
+/* CPU identification */
+u32 cpu_family_model(void);
+u32 cpu_stepping(void);
+int cpu_is_ult(void);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
new file mode 100644
index 0000000..7dab40d
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_DEVICE_NVS_H_
+#define _BROADWELL_DEVICE_NVS_H_
+
+#include <stdint.h>
+
+/* Offset in Global NVS where this structure lives */
+#define DEVICE_NVS_OFFSET 0x1000
+
+#define SIO_NVS_DMA 0
+#define SIO_NVS_I2C0 1
+#define SIO_NVS_I2C1 2
+#define SIO_NVS_SPI0 3
+#define SIO_NVS_SPI1 4
+#define SIO_NVS_UART0 5
+#define SIO_NVS_UART1 6
+#define SIO_NVS_SDIO 7
+#define SIO_NVS_ADSP 8
+
+typedef struct {
+ u8 enable[9];
+ u32 bar0[9];
+ u32 bar1[9];
+} __attribute__((packed)) device_nvs_t;
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/ehci.h b/src/soc/intel/broadwell/include/soc/ehci.h
new file mode 100644
index 0000000..44d51ef
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/ehci.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_EHCI_H_
+#define _BROADWELL_EHCI_H_
+
+/* EHCI Memory Registers */
+#define EHCI_USB_CMD 0x20
+#define EHCI_USB_CMD_RUN (1 << 0)
+#define EHCI_USB_CMD_PSE (1 << 4)
+#define EHCI_USB_CMD_ASE (1 << 5)
+#define EHCI_PORTSC(port) (0x64 + (port * 4))
+#define EHCI_PORTSC_ENABLED (1 << 2)
+#define EHCI_PORTSC_SUSPEND (1 << 7)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h
new file mode 100644
index 0000000..a035975
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/gpio.h
@@ -0,0 +1,192 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_GPIO_H_
+#define _BROADWELL_GPIO_H_
+
+#include <stdint.h>
+
+/* PCH-LP GPIOBASE Registers */
+#define GPIO_OWNER(set) (0x00 + ((set) * 4))
+#define GPIO_PIRQ_APIC_EN 0x10
+#define GPIO_BLINK 0x18
+#define GPIO_SER_BLINK 0x1c
+#define GPIO_SER_BLINK_CS 0x20
+#define GPIO_SER_BLINK_DATA 0x24
+#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
+#define GPIO_ALT_GPI_SMI_STS 0x50
+#define GPIO_ALT_GPI_SMI_EN 0x54
+#define GPIO_RESET(set) (0x60 + ((set) * 4))
+#define GPIO_GLOBAL_CONFIG 0x7c
+#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
+#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4))
+#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8))
+#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
+
+#define MAX_GPIO_NUMBER 94 /* zero based */
+#define GPIO_LIST_END 0xffffffff
+
+/* conf0 */
+
+#define GPIO_MODE_NATIVE (0 << 0)
+#define GPIO_MODE_GPIO (1 << 0)
+
+#define GPIO_DIR_OUTPUT (0 << 2)
+#define GPIO_DIR_INPUT (1 << 2)
+
+#define GPIO_NO_INVERT (0 << 3)
+#define GPIO_INVERT (1 << 3)
+
+#define GPIO_IRQ_EDGE (0 << 4)
+#define GPIO_IRQ_LEVEL (1 << 4)
+
+#define GPI_LEVEL (1 << 30)
+
+#define GPIO_OUT_LOW 0
+#define GPIO_OUT_HIGH 1
+#define GPO_LEVEL_SHIFT 31
+#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_LOW (GPIO_OUT_LOW << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_HIGH (GPIO_OUT_HIGH << GPO_LEVEL_SHIFT)
+
+/* conf1 */
+
+#define GPIO_PULL_NONE (0 << 0)
+#define GPIO_PULL_DOWN (1 << 0)
+#define GPIO_PULL_UP (2 << 0)
+
+#define GPIO_SENSE_ENABLE (0 << 2)
+#define GPIO_SENSE_DISABLE (1 << 2)
+
+/* owner */
+
+#define GPIO_OWNER_ACPI 0
+#define GPIO_OWNER_GPIO 1
+
+/* route */
+
+#define GPIO_ROUTE_SCI 0
+#define GPIO_ROUTE_SMI 1
+
+/* irqen */
+
+#define GPIO_IRQ_DISABLE 0
+#define GPIO_IRQ_ENABLE 1
+
+/* blink */
+
+#define GPO_NO_BLINK 0
+#define GPO_BLINK 1
+
+/* reset */
+
+#define GPIO_RESET_PWROK 0
+#define GPIO_RESET_RSMRST 1
+
+/* pirq route to io-apic */
+
+#define GPIO_PIRQ_APIC_MASK 0
+#define GPIO_PIRQ_APIC_ROUTE 1
+
+#define PCH_GPIO_END \
+ { .conf0 = GPIO_LIST_END }
+
+#define PCH_GPIO_NATIVE \
+ { .conf0 = GPIO_MODE_NATIVE }
+
+#define PCH_GPIO_UNUSED \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
+ .owner = GPIO_OWNER_GPIO, \
+ .conf1 = GPIO_SENSE_DISABLE }
+
+#define PCH_GPIO_ACPI_SCI \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
+ .owner = GPIO_OWNER_ACPI, \
+ .route = GPIO_ROUTE_SCI }
+
+#define PCH_GPIO_ACPI_SMI \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
+ .owner = GPIO_OWNER_ACPI, \
+ .route = GPIO_ROUTE_SMI }
+
+#define PCH_GPIO_INPUT \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
+ .owner = GPIO_OWNER_GPIO }
+
+#define PCH_GPIO_INPUT_INVERT \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
+ .owner = GPIO_OWNER_GPIO }
+
+#define PCH_GPIO_IRQ_EDGE \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \
+ .owner = GPIO_OWNER_GPIO, \
+ .irqen = GPIO_IRQ_ENABLE }
+
+#define PCH_GPIO_IRQ_LEVEL \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \
+ .owner = GPIO_OWNER_GPIO, \
+ .irqen = GPIO_IRQ_ENABLE }
+
+#define PCH_GPIO_PIRQ \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
+ .owner = GPIO_OWNER_GPIO, \
+ .pirq = GPIO_PIRQ_APIC_ROUTE }
+
+#define PCH_GPIO_OUT_HIGH \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \
+ .owner = GPIO_OWNER_GPIO, \
+ .conf1 = GPIO_SENSE_DISABLE }
+
+#define PCH_GPIO_OUT_LOW \
+ { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \
+ .owner = GPIO_OWNER_GPIO, \
+ .conf1 = GPIO_SENSE_DISABLE }
+
+struct gpio_config {
+ u8 gpio;
+ u32 conf0;
+ u32 conf1;
+ u8 owner;
+ u8 route;
+ u8 irqen;
+ u8 reset;
+ u8 blink;
+ u8 pirq;
+} __attribute__ ((packed));
+
+/* Configure GPIOs with mainboard provided settings */
+void init_one_gpio(int gpio_num, struct gpio_config *config);
+void init_gpios(const struct gpio_config config[]);
+
+/* Get GPIO pin value */
+int get_gpio(int gpio_num);
+
+/* Set GPIO pin value */
+void set_gpio(int gpio_num, int value);
+
+/* Return non-zero if gpio is set to native function. 0 otherwise. */
+int gpio_is_native(int gpio_num);
+
+/*
+ * Get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/soc/intel/broadwell/include/soc/iobp.h
new file mode 100644
index 0000000..9f17692
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/iobp.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_IOBP_H_
+#define _BROADWELL_IOBP_H_
+
+u32 pch_iobp_read(u32 address);
+void pch_iobp_write(u32 address, u32 data);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h
new file mode 100644
index 0000000..bb98975
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/iomap.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_IOMAP_H_
+#define _BROADWELL_IOMAP_H_
+
+#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE 0x4000000
+
+#define MCH_BASE_ADDRESS 0xfed10000
+#define MCH_BASE_SIZE 0x8000
+
+#define DMI_BASE_ADDRESS 0xfed18000
+#define DMI_BASE_SIZE 0x1000
+
+#define EP_BASE_ADDRESS 0xfed19000
+#define EP_BASE_SIZE 0x1000
+
+#define EDRAM_BASE_ADDRESS 0xfed80000
+#define EDRAM_BASE_SIZE 0x4000
+
+#define GDXC_BASE_ADDRESS 0xfed84000
+#define GDXC_BASE_SIZE 0x1000
+
+#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x4000
+
+#define HPET_BASE_ADDRESS 0xfed00000
+
+#define ACPI_BASE_ADDRESS 0x1000
+#define ACPI_BASE_SIZE 0x100
+
+#define GPIO_BASE_ADDRESS 0x1400
+#define GPIO_BASE_SIZE 0x400
+
+#define SMBUS_BASE_ADDRESS 0x0400
+#define SMBUS_BASE_SIZE 0x10
+
+/* Temporary addresses used in romstage */
+#define EARLY_GTT_BAR 0xe0000000
+#define EARLY_XHCI_BAR 0xd7000000
+#define EARLY_EHCI_BAR CONFIG_EHCI_BAR
+#define EARLY_UART_BAR CONFIG_TTYS0_BASE
+#define EARLY_TEMP_MMIO 0xfed08000
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/lpc.h b/src/soc/intel/broadwell/include/soc/lpc.h
new file mode 100644
index 0000000..180e527
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/lpc.h
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_LPC_H_
+#define _BROADWELL_LPC_H_
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define SERIRQ_CNTL 0x64
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 7)
+#define SCI_IRQ_SEL (7 << 0)
+#define SCIS_IRQ9 0
+#define SCIS_IRQ10 1
+#define SCIS_IRQ11 2
+#define SCIS_IRQ20 4
+#define SCIS_IRQ21 5
+#define SCIS_IRQ22 6
+#define SCIS_IRQ23 7
+#define GPIOBASE 0x48
+#define BIOS_CNTL 0xdc
+#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_EN (1 << 4)
+#define GPIO_ROUT 0xb8
+
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x68
+#define PIRQF_ROUT 0x69
+#define PIRQG_ROUT 0x6A
+#define PIRQH_ROUT 0x6B
+
+#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
+#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
+#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
+#define LGMR 0x98 /* LPC Generic Memory Range */
+#define RCBA 0xf0 /* Root Complex Register Block */
+
+/* Power Management */
+
+#define GEN_PMCON_1 0xa0
+#define SMI_LOCK (1 << 4)
+#define GEN_PMCON_2 0xa2
+#define SYSTEM_RESET_STS (1 << 4)
+#define THERMTRIP_STS (1 << 3)
+#define SYSPWR_FLR (1 << 1)
+#define PWROK_FLR (1 << 0)
+#define GEN_PMCON_3 0xa4
+#define SUS_PWR_FLR (1 << 14)
+#define GEN_RST_STS (1 << 9)
+#define RTC_BATTERY_DEAD (1 << 2)
+#define PWR_FLR (1 << 1)
+#define SLEEP_AFTER_POWER_FAIL (1 << 0)
+#define GEN_PMCON_LOCK 0xa6
+#define SLP_STR_POL_LOCK (1 << 2)
+#define ACPI_BASE_LOCK (1 << 1)
+#define PMIR 0xac
+#define PMIR_CF9LOCK (1 << 31)
+#define PMIR_CF9GR (1 << 20)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/me.h b/src/soc/intel/broadwell/include/soc/me.h
new file mode 100644
index 0000000..a69dfd5
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/me.h
@@ -0,0 +1,508 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_ME_H_
+#define _BROADWELL_ME_H_
+
+#include <console/loglevel.h>
+
+#define ME_RETRY 100000 /* 1 second */
+#define ME_DELAY 10 /* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
+#define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
+
+#define PCI_ME_HFS 0x40
+#define ME_HFS_CWS_RESET 0
+#define ME_HFS_CWS_INIT 1
+#define ME_HFS_CWS_REC 2
+#define ME_HFS_CWS_NORMAL 5
+#define ME_HFS_CWS_WAIT 6
+#define ME_HFS_CWS_TRANS 7
+#define ME_HFS_CWS_INVALID 8
+#define ME_HFS_STATE_PREBOOT 0
+#define ME_HFS_STATE_M0_UMA 1
+#define ME_HFS_STATE_M3 4
+#define ME_HFS_STATE_M0 5
+#define ME_HFS_STATE_BRINGUP 6
+#define ME_HFS_STATE_ERROR 7
+#define ME_HFS_ERROR_NONE 0
+#define ME_HFS_ERROR_UNCAT 1
+#define ME_HFS_ERROR_IMAGE 3
+#define ME_HFS_ERROR_DEBUG 4
+#define ME_HFS_MODE_NORMAL 0
+#define ME_HFS_MODE_DEBUG 2
+#define ME_HFS_MODE_DIS 3
+#define ME_HFS_MODE_OVER_JMPR 4
+#define ME_HFS_MODE_OVER_MEI 5
+#define ME_HFS_BIOS_DRAM_ACK 1
+#define ME_HFS_ACK_NO_DID 0
+#define ME_HFS_ACK_RESET 1
+#define ME_HFS_ACK_PWR_CYCLE 2
+#define ME_HFS_ACK_S3 3
+#define ME_HFS_ACK_S4 4
+#define ME_HFS_ACK_S5 5
+#define ME_HFS_ACK_GBL_RESET 6
+#define ME_HFS_ACK_CONTINUE 7
+
+struct me_hfs {
+ u32 working_state: 4;
+ u32 mfg_mode: 1;
+ u32 fpt_bad: 1;
+ u32 operation_state: 3;
+ u32 fw_init_complete: 1;
+ u32 ft_bup_ld_flr: 1;
+ u32 update_in_progress: 1;
+ u32 error_code: 4;
+ u32 operation_mode: 4;
+ u32 reserved: 4;
+ u32 boot_options_present: 1;
+ u32 ack_data: 3;
+ u32 bios_msg_ack: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_UMA 0x44
+
+struct me_uma {
+ u32 size: 6;
+ u32 reserved_1: 10;
+ u32 valid: 1;
+ u32 reserved_0: 14;
+ u32 set_to_one: 1;
+} __attribute__ ((packed));
+
+#define PCI_ME_H_GS 0x4c
+#define ME_INIT_DONE 1
+#define ME_INIT_STATUS_SUCCESS 0
+#define ME_INIT_STATUS_NOMEM 1
+#define ME_INIT_STATUS_ERROR 2
+#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
+
+#define ME_HSIO_MESSAGE (7 << 28)
+#define ME_HSIO_CMD_GETHSIOVER 1
+#define ME_HSIO_CMD_CLOSE 0
+
+struct me_did {
+ u32 uma_base: 16;
+ u32 reserved: 7;
+ u32 rapid_start: 1;
+ u32 status: 4;
+ u32 init_done: 4;
+} __attribute__ ((packed));
+
+/*
+ * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
+ * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
+ */
+#define PCI_ME_HFS2 0x48
+/* Infrastructure Progress Values */
+#define ME_HFS2_PHASE_ROM 0
+#define ME_HFS2_PHASE_BUP 1
+#define ME_HFS2_PHASE_UKERNEL 2
+#define ME_HFS2_PHASE_POLICY 3
+#define ME_HFS2_PHASE_MODULE_LOAD 4
+#define ME_HFS2_PHASE_UNKNOWN 5
+#define ME_HFS2_PHASE_HOST_COMM 6
+/* Current State - Based on Infra Progress values. */
+/* ROM State */
+#define ME_HFS2_STATE_ROM_BEGIN 0
+#define ME_HFS2_STATE_ROM_DISABLE 6
+/* BUP State */
+#define ME_HFS2_STATE_BUP_INIT 0
+#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
+#define ME_HFS2_STATE_BUP_FLOW_DET 4
+#define ME_HFS2_STATE_BUP_VSCC_ERR 8
+#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
+#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
+#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
+#define ME_HFS2_STATE_BUP_M3 0x11
+#define ME_HFS2_STATE_BUP_M0 0x12
+#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
+#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
+#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
+#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
+#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
+#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
+#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
+#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
+#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
+#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
+#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
+#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
+#define ME_HFS2_STATE_BUP_M0_CLK 0x26
+#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
+#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
+#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
+/* Policy Module State */
+#define ME_HFS2_STATE_POLICY_ENTRY 0
+#define ME_HFS2_STATE_POLICY_RCVD_S3 3
+#define ME_HFS2_STATE_POLICY_RCVD_S4 4
+#define ME_HFS2_STATE_POLICY_RCVD_S5 5
+#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
+#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
+#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
+#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
+#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
+#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
+#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
+#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
+#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
+#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
+#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
+/* Current PM Event Values */
+#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
+#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
+#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
+#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
+#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
+#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
+#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
+#define ME_HFS2_PMEVENT_S0MO_SXM3 7
+#define ME_HFS2_PMEVENT_SXM3_S0M0 8
+#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
+#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
+#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
+#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
+
+struct me_hfs2 {
+ u32 bist_in_progress: 1;
+ u32 reserved1: 2;
+ u32 invoke_mebx: 1;
+ u32 cpu_replaced_sts: 1;
+ u32 mbp_rdy: 1;
+ u32 mfs_failure: 1;
+ u32 warm_reset_request: 1;
+ u32 cpu_replaced_valid: 1;
+ u32 reserved2: 4;
+ u32 mbp_cleared: 1;
+ u32 reserved3: 2;
+ u32 current_state: 8;
+ u32 current_pmevent: 4;
+ u32 progress_code: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_HFS5 0x68
+
+#define PCI_ME_H_GS2 0x70
+#define PCI_ME_MBP_GIVE_UP 0x01
+
+#define PCI_ME_HERES 0xbc
+#define PCI_ME_EXT_SHA1 0x00
+#define PCI_ME_EXT_SHA256 0x02
+#define PCI_ME_HER(x) (0xc0+(4*(x)))
+
+struct me_heres {
+ u32 extend_reg_algorithm: 4;
+ u32 reserved: 26;
+ u32 extend_feature_present: 1;
+ u32 extend_reg_valid: 1;
+} __attribute__ ((packed));
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW 0x00
+#define MEI_H_CSR 0x04
+#define MEI_ME_CB_RW 0x08
+#define MEI_ME_CSR_HA 0x0c
+
+struct mei_csr {
+ u32 interrupt_enable: 1;
+ u32 interrupt_status: 1;
+ u32 interrupt_generate: 1;
+ u32 ready: 1;
+ u32 reset: 1;
+ u32 reserved: 3;
+ u32 buffer_read_ptr: 8;
+ u32 buffer_write_ptr: 8;
+ u32 buffer_depth: 8;
+} __attribute__ ((packed));
+
+#define MEI_ADDRESS_CORE 0x01
+#define MEI_ADDRESS_AMT 0x02
+#define MEI_ADDRESS_RESERVED 0x03
+#define MEI_ADDRESS_WDT 0x04
+#define MEI_ADDRESS_MKHI 0x07
+#define MEI_ADDRESS_ICC 0x08
+#define MEI_ADDRESS_THERMAL 0x09
+
+#define MEI_HOST_ADDRESS 0
+
+struct mei_header {
+ u32 client_address: 8;
+ u32 host_address: 8;
+ u32 length: 9;
+ u32 reserved: 6;
+ u32 is_complete: 1;
+} __attribute__ ((packed));
+
+#define MKHI_GROUP_ID_CBM 0x00
+#define MKHI_GROUP_ID_FWCAPS 0x03
+#define MKHI_GROUP_ID_MDES 0x08
+#define MKHI_GROUP_ID_GEN 0xff
+
+#define MKHI_GLOBAL_RESET 0x0b
+
+#define MKHI_FWCAPS_GET_RULE 0x02
+
+#define MKHI_MDES_ENABLE 0x09
+
+#define MKHI_GET_FW_VERSION 0x02
+#define MKHI_END_OF_POST 0x0c
+#define MKHI_FEATURE_OVERRIDE 0x14
+
+struct mkhi_header {
+ u32 group_id: 8;
+ u32 command: 7;
+ u32 is_response: 1;
+ u32 reserved: 8;
+ u32 result: 8;
+} __attribute__ ((packed));
+
+struct me_fw_version {
+ u16 code_minor;
+ u16 code_major;
+ u16 code_build_number;
+ u16 code_hot_fix;
+ u16 recovery_minor;
+ u16 recovery_major;
+ u16 recovery_build_number;
+ u16 recovery_hot_fix;
+} __attribute__ ((packed));
+
+/* ICC Messages */
+#define ICC_SET_CLOCK_ENABLES 0x3
+#define ICC_API_VERSION_LYNXPOINT 0x00030000
+
+struct icc_header {
+ u32 api_version;
+ u32 icc_command;
+ u32 icc_status;
+ u32 length;
+ u32 reserved;
+} __attribute__ ((packed));
+
+struct icc_clock_enables_msg {
+ u32 clock_enables;
+ u32 clock_mask;
+ u32 no_response: 1;
+ u32 reserved: 31;
+} __attribute__ ((packed));
+
+#define HECI_EOP_STATUS_SUCCESS 0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET 0x01
+
+#define GLOBAL_RESET_BIOS_MRC 0x01
+#define GLOBAL_RESET_BIOS_POST 0x02
+#define GLOBAL_RESET_MEBX 0x03
+
+struct me_global_reset {
+ u8 request_origin;
+ u8 reset_type;
+} __attribute__ ((packed));
+
+typedef enum {
+ ME_NORMAL_BIOS_PATH,
+ ME_S3WAKE_BIOS_PATH,
+ ME_ERROR_BIOS_PATH,
+ ME_RECOVERY_BIOS_PATH,
+ ME_DISABLE_BIOS_PATH,
+ ME_FIRMWARE_UPDATE_BIOS_PATH,
+} me_bios_path;
+
+/*
+ * ME to BIOS Payload Datastructures and definitions. The ordering of the
+ * structures follows the ordering in the ME9 BWG.
+ */
+
+#define MBP_APPID_KERNEL 1
+#define MBP_APPID_INTEL_AT 3
+#define MBP_APPID_HWA 4
+#define MBP_APPID_ICC 5
+#define MBP_APPID_NFC 6
+/* Kernel items: */
+#define MBP_KERNEL_FW_VER_ITEM 1
+#define MBP_KERNEL_FW_CAP_ITEM 2
+#define MBP_KERNEL_ROM_BIST_ITEM 3
+#define MBP_KERNEL_PLAT_KEY_ITEM 4
+#define MBP_KERNEL_FW_TYPE_ITEM 5
+#define MBP_KERNEL_MFS_FAILURE_ITEM 6
+#define MBP_KERNEL_PLAT_TIME_ITEM 7
+/* Intel AT items: */
+#define MBP_INTEL_AT_STATE_ITEM 1
+/* ICC Items: */
+#define MBP_ICC_PROFILE_ITEM 1
+/* HWA Items: */
+#define MBP_HWA_REQUEST_ITEM 1
+/* NFC Items: */
+#define MBP_NFC_SUPPORT_DATA_ITEM 1
+
+#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
+#define MBP_IDENT(appid, item) \
+ MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
+
+typedef struct {
+ u32 mbp_size : 8;
+ u32 num_entries : 8;
+ u32 rsvd : 16;
+} __attribute__ ((packed)) mbp_header;
+
+typedef struct {
+ u32 app_id : 8;
+ u32 item_id : 8;
+ u32 length : 8;
+ u32 rsvd : 8;
+} __attribute__ ((packed)) mbp_item_header;
+
+typedef struct {
+ u32 major_version : 16;
+ u32 minor_version : 16;
+ u32 hotfix_version : 16;
+ u32 build_version : 16;
+} __attribute__ ((packed)) mbp_fw_version_name;
+
+typedef struct {
+ u32 full_net : 1;
+ u32 std_net : 1;
+ u32 manageability : 1;
+ u32 reserved_2 : 2;
+ u32 intel_at : 1;
+ u32 intel_cls : 1;
+ u32 reserved : 3;
+ u32 intel_mpc : 1;
+ u32 icc_over_clocking : 1;
+ u32 pavp : 1;
+ u32 reserved_1 : 4;
+ u32 ipv6 : 1;
+ u32 kvm : 1;
+ u32 och : 1;
+ u32 vlan : 1;
+ u32 tls : 1;
+ u32 reserved_4 : 1;
+ u32 wlan : 1;
+ u32 reserved_5 : 8;
+} __attribute__ ((packed)) mbp_mefwcaps;
+
+typedef struct {
+ u16 device_id;
+ u16 fuse_test_flags;
+ u32 umchid[4];
+} __attribute__ ((packed)) mbp_rom_bist_data;
+
+typedef struct {
+ u32 key[8];
+} mbp_platform_key;
+
+typedef struct {
+ u32 mobile: 1;
+ u32 desktop: 1;
+ u32 server: 1;
+ u32 workstation: 1;
+ u32 corporate: 1;
+ u32 consumer: 1;
+ u32 regular_super_sku: 1;
+ u32 rsvd: 1;
+ u32 image_type: 4;
+ u32 brand: 4;
+ u32 rsvd1: 16;
+} __attribute__ ((packed)) mbp_me_firmware_type;
+
+typedef struct {
+ mbp_me_firmware_type rule_data;
+ u8 available;
+} mbp_plat_type;
+
+typedef struct {
+ u16 icc_start_address;
+ u16 mask;
+} __attribute__ ((packed)) icc_address_mask;
+
+typedef struct {
+ u8 num_icc_profiles;
+ u8 icc_profile_soft_strap;
+ u8 icc_profile_index;
+ u8 reserved;
+ u32 icc_reg_bundles;
+ icc_address_mask icc_address_mask[0];
+} __attribute__ ((packed)) mbp_icc_profile;
+
+typedef struct {
+ u16 lock_state : 1;
+ u16 authenticate_module : 1;
+ u16 s3authentication : 1;
+ u16 flash_wear_out : 1;
+ u16 flash_variable_security : 1;
+ u16 reserved : 11;
+} __attribute__ ((packed)) tdt_state_flag;
+
+typedef struct {
+ u8 state;
+ u8 last_theft_trigger;
+ tdt_state_flag flags;
+} __attribute__ ((packed)) mbp_at_state;
+
+typedef struct {
+ u32 wake_event_mrst_time_ms;
+ u32 mrst_pltrst_time_ms;
+ u32 pltrst_cpurst_time_ms;
+} __attribute__ ((packed)) mbp_plat_time;
+
+typedef struct {
+ u32 device_type : 2;
+ u32 reserved : 30;
+} __attribute__ ((packed)) mbp_nfc_data;
+
+typedef struct {
+ mbp_fw_version_name *fw_version_name;
+ mbp_mefwcaps *fw_capabilities;
+ mbp_rom_bist_data *rom_bist_data;
+ mbp_platform_key *platform_key;
+ mbp_plat_type *fw_plat_type;
+ mbp_icc_profile *icc_profile;
+ mbp_at_state *at_state;
+ u32 *mfsintegrity;
+ mbp_plat_time *plat_time;
+ mbp_nfc_data *nfc_data;
+} me_bios_payload;
+
+struct me_fwcaps {
+ u32 id;
+ u8 length;
+ mbp_mefwcaps caps_sku;
+ u8 reserved[3];
+} __attribute__ ((packed));
+
+void intel_me_finalize(void);
+void intel_me_hsio_version(uint16_t *version, uint16_t *checksum);
+
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+/* Defined in me_status.c for both romstage and ramstage */
+void intel_me_status(void);
+#else
+static inline void intel_me_status(void) { }
+#endif
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
new file mode 100644
index 0000000..707041a
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_MSR_H_
+#define _BROADWELL_MSR_H_
+
+#define MSR_PIC_MSG_CONTROL 0x2e
+#define CORE_THREAD_COUNT_MSR 0x35
+#define IA32_FEATURE_CONTROL 0x3a
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+#define MSR_PLATFORM_INFO 0xce
+#define PLATFORM_INFO_SET_TDP (1 << 29)
+#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PMG_IO_CAPTURE_BASE 0xe4
+#define MSR_FEATURE_CONFIG 0x13c
+#define SMM_MCA_CAP_MSR 0x17d
+#define SMM_CPU_SVRSTR_BIT 57
+#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
+#define IA32_MISC_ENABLE 0x1a0
+#define MSR_MISC_PWR_MGMT 0x1aa
+#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
+#define MSR_TURBO_RATIO_LIMIT 0x1ad
+#define MSR_TEMPERATURE_TARGET 0x1a2
+#define IA32_PERF_CTL 0x199
+#define IA32_THERM_INTERRUPT 0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
+#define ENERGY_POLICY_PERFORMANCE 0
+#define ENERGY_POLICY_NORMAL 6
+#define ENERGY_POLICY_POWERSAVE 15
+#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
+#define EMRRphysBase_MSR 0x1f4
+#define EMRRphysMask_MSR 0x1f5
+#define IA32_PLATFORM_DCA_CAP 0x1f8
+#define MSR_POWER_CTL 0x1fc
+#define MSR_LT_LOCK_MEMORY 0x2e7
+#define UNCORE_EMRRphysBase_MSR 0x2f4
+#define UNCORE_EMRRphysMask_MSR 0x2f5
+#define IA32_MC0_STATUS 0x401
+#define SMM_FEATURE_CONTROL_MSR 0x4e0
+#define SMM_CPU_SAVE_EN (1 << 1)
+
+#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3 0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4 0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5 0x635
+#define IRTL_VALID (1 << 15)
+#define IRTL_1_NS (0 << 10)
+#define IRTL_32_NS (1 << 10)
+#define IRTL_1024_NS (2 << 10)
+#define IRTL_32768_NS (3 << 10)
+#define IRTL_1048576_NS (4 << 10)
+#define IRTL_33554432_NS (5 << 10)
+#define IRTL_RESPONSE_MASK (0x3ff)
+#define MSR_COUNTER_24_MHZ 0x637
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT 0x610
+#define PKG_POWER_LIMIT_MASK 0x7fff
+#define PKG_POWER_LIMIT_EN (1 << 15)
+#define PKG_POWER_LIMIT_CLAMP (1 << 16)
+#define PKG_POWER_LIMIT_TIME_SHIFT 17
+#define PKG_POWER_LIMIT_TIME_MASK 0x7f
+
+#define MSR_VR_CURRENT_CONFIG 0x601
+#define MSR_VR_MISC_CONFIG 0x603
+#define MSR_PKG_POWER_SKU_UNIT 0x606
+#define MSR_PKG_POWER_SKU 0x614
+#define MSR_DDR_RAPL_LIMIT 0x618
+#define MSR_VR_MISC_CONFIG2 0x636
+#define MSR_PP0_POWER_LIMIT 0x638
+#define MSR_PP1_POWER_LIMIT 0x640
+
+#define MSR_CONFIG_TDP_NOMINAL 0x648
+#define MSR_CONFIG_TDP_LEVEL1 0x649
+#define MSR_CONFIG_TDP_LEVEL2 0x64a
+#define MSR_CONFIG_TDP_CONTROL 0x64b
+#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+
+/* SMM save state MSRs */
+#define SMBASE_MSR 0xc20
+#define IEDBASE_MSR 0xc22
+
+/* MTRRcap_MSR bits */
+#define SMRR_SUPPORTED (1<<11)
+#define EMRR_SUPPORTED (1<<12)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
new file mode 100644
index 0000000..41b2e4a
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_NVS_H_
+#define _BROADWELL_NVS_H_
+
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <soc/device_nvs.h>
+
+typedef struct {
+ /* Miscellaneous */
+ u16 osys; /* 0x00 - Operating System */
+ u8 smif; /* 0x02 - SMI function call ("TRAP") */
+ u8 prm0; /* 0x03 - SMI function call parameter */
+ u8 prm1; /* 0x04 - SMI function call parameter */
+ u8 scif; /* 0x05 - SCI function call (via _L00) */
+ u8 prm2; /* 0x06 - SCI function call parameter */
+ u8 prm3; /* 0x07 - SCI function call parameter */
+ u8 lckf; /* 0x08 - Global Lock function for EC */
+ u8 prm4; /* 0x09 - Lock function parameter */
+ u8 prm5; /* 0x0a - Lock function parameter */
+ u8 pcnt; /* 0x0b - Processor Count */
+ u8 ppcm; /* 0x0c - Max PPC State */
+ u8 tmps; /* 0x0d - Temperature Sensor ID */
+ u8 tlvl; /* 0x0e - Throttle Level Limit */
+ u8 flvl; /* 0x0f - Current FAN Level */
+ u8 tcrt; /* 0x10 - Critical Threshold */
+ u8 tpsv; /* 0x11 - Passive Threshold */
+ u8 tmax; /* 0x12 - CPU Tj_max */
+ u8 tpmp; /* 0x13 - TPM Present */
+ u8 s5u0; /* 0x14 - Enable USB in S5 */
+ u8 s3u0; /* 0x15 - Enable USB in S3 */
+ u8 s33g; /* 0x16 - Enable 3G in S3 */
+ u8 lids; /* 0x17 - LID State */
+ u8 pwrs; /* 0x18 - AC Power State */
+ u32 obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */
+ u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
+ u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
+ u8 rsvd3[219];
+
+ /* ChromeOS specific (0x100 - 0xfff) */
+ chromeos_acpi_t chromeos;
+
+ /* Device specific (0x1000) */
+ device_nvs_t dev;
+} __attribute__((packed)) global_nvs_t;
+
+void acpi_create_gnvs(global_nvs_t *gnvs);
+#ifdef __SMM__
+/* Used in SMM to find the ACPI GNVS address */
+global_nvs_t *smm_get_gnvs(void);
+#endif
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h
new file mode 100644
index 0000000..e677215
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/pch.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_PCH_H_
+#define _BROADWELL_PCH_H_
+
+/* Haswell ULT Pch (LynxPoint-LP) */
+#define PCH_LPT_LP_SAMPLE 0x9c41
+#define PCH_LPT_LP_PREMIUM 0x9c43
+#define PCH_LPT_LP_MAINSTREAM 0x9c45
+#define PCH_LPT_LP_VALUE 0x9c47
+
+/* Broadwell PCH (WildatPoint) */
+#define PCH_WPT_HSW_U_SAMPLE 0x9cc1
+#define PCH_WPT_BDW_U_SAMPLE 0x9cc2
+#define PCH_WPT_BDW_U_PREMIUM 0x9cc3
+#define PCH_WPT_BDW_U_BASE 0x9cc5
+#define PCH_WPT_BDW_Y_SAMPLE 0x9cc6
+#define PCH_WPT_BDW_Y_PREMIUM 0x9cc7
+#define PCH_WPT_BDW_Y_BASE 0x9cc9
+#define PCH_WPT_BDW_H 0x9ccb
+
+/* Power Management Control and Status */
+#define PCH_PCS 0x84
+#define PCH_PCS_PS_D3HOT 3
+
+u8 pch_revision(void);
+u16 pch_type(void);
+int pch_is_wpt(void);
+int pch_is_wpt_ulx(void);
+u32 pch_read_soft_strap(int id);
+void pch_log_state(void);
+void pch_disable_devfn(device_t dev);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h
new file mode 100644
index 0000000..76e3a68
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/pci_devs.h
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_PCI_DEVS_H_
+#define _BROADWELL_PCI_DEVS_H_
+
+#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEVFN(slot,func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
+
+#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
+#include <arch/io.h>
+#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
+#define _PCH_DEV(slot,func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#else
+#include <device/device.h>
+#include <device/pci_def.h>
+#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
+#define _PCH_DEV(slot,func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#endif
+
+/* System Agent Devices */
+
+#define SA_DEV_SLOT_ROOT 0x00
+#define SA_DEVFN_ROOT _SA_DEVFN(ROOT)
+#define SA_DEV_ROOT _SA_DEV(ROOT)
+
+#define SA_DEV_SLOT_IGD 0x02
+#define SA_DEVFN_IGD _SA_DEVFN(IGD)
+#define SA_DEV_IGD _SA_DEV(IGD)
+
+#define SA_DEV_SLOT_MINIHD 0x03
+#define SA_DEVFN_MINIHD _SA_DEVFN(MINIHD)
+#define SA_DEV_MINIHD _SA_DEV(MINIHD)
+
+/* PCH Devices */
+
+#define PCH_DEV_SLOT_ADSP 0x13
+#define PCH_DEVFN_ADSP _PCH_DEVFN(ADSP, 0)
+#define PCH_DEV_ADSP _PCH_DEV(ADSP, 0)
+
+#define PCH_DEV_SLOT_XHCI 0x14
+#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
+#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
+
+#define PCH_DEV_SLOT_SIO 0x15
+#define PCH_DEV_SDMA _PCH_DEV(SIO, 0)
+#define PCH_DEV_I2C0 _PCH_DEV(SIO, 1)
+#define PCH_DEV_I2C1 _PCH_DEV(SIO, 2)
+#define PCH_DEV_SPI0 _PCH_DEV(SIO, 3)
+#define PCH_DEV_SPI1 _PCH_DEV(SIO, 4)
+#define PCH_DEV_UART0 _PCH_DEV(SIO, 5)
+#define PCH_DEV_UART1 _PCH_DEV(SIO, 6)
+#define PCH_DEVFN_SDMA _PCH_DEVFN(SIO, 0)
+#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO, 1)
+#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO, 2)
+#define PCH_DEVFN_SPI0 _PCH_DEVFN(SIO, 3)
+#define PCH_DEVFN_SPI1 _PCH_DEVFN(SIO, 4)
+#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO, 5)
+#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO, 6)
+
+#define PCH_DEV_SLOT_ME 0x16
+#define PCH_DEVFN_ME _PCH_DEVFN(ME, 0)
+#define PCH_DEVFN_ME_2 _PCH_DEVFN(ME, 1)
+#define PCH_DEVFN_ME_IDER _PCH_DEVFN(ME, 2)
+#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3)
+#define PCH_DEV_ME _PCH_DEV(ME, 0)
+#define PCH_DEV_ME_2 _PCH_DEV(ME, 1)
+#define PCH_DEV_ME_IDER _PCH_DEV(ME, 2)
+#define PCH_DEV_ME_KT _PCH_DEV(ME, 3)
+
+#define PCH_DEV_SLOT_SDIO 0x17
+#define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0)
+#define PCH_DEV_SDIO _PCH_DEV(SDIO, 0)
+
+#define PCH_DEV_SLOT_GBE 0x19
+#define PCH_DEVFN_GBE _PCH_DEVFN(GBE, 0)
+#define PCH_DEV_GBE _PCH_DEV(GBE, 0)
+
+#define PCH_DEV_SLOT_HDA 0x1b
+#define PCH_DEVFN_HDA _PCH_DEVFN(HDA, 0)
+#define PCH_DEV_HDA _PCH_DEV(HDA, 0)
+
+#define PCH_DEV_SLOT_PCIE 0x1c
+
+#define PCH_DEV_SLOT_EHCI 0x1d
+#define PCH_DEVFN_EHCI _PCH_DEVFN(EHCI, 0)
+#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0)
+
+#define PCH_DEV_SLOT_LPC 0x1f
+#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
+#define PCH_DEVFN_IDE _PCH_DEVFN(LPC, 1)
+#define PCH_DEVFN_SATA _PCH_DEVFN(LPC, 2)
+#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 3)
+#define PCH_DEVFN_SATA2 _PCH_DEVFN(LPC, 5)
+#define PCH_DEVFN_THERMAL _PCH_DEVFN(LPC, 6)
+#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
+#define PCH_DEV_IDE _PCH_DEV(LPC, 1)
+#define PCH_DEV_SATA _PCH_DEV(LPC, 2)
+#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3)
+#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5)
+#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/pei_data.h b/src/soc/intel/broadwell/include/soc/pei_data.h
new file mode 100644
index 0000000..e614718
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/pei_data.h
@@ -0,0 +1,199 @@
+/*
+ * Broadwell UEFI PEI wrapper
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PEI_DATA_H
+#define PEI_DATA_H
+
+#include <types.h>
+#include <memory_info.h>
+
+#define PEI_VERSION 22
+
+#define ABI_X86 __attribute__((regparm(0)))
+
+typedef void ABI_X86 (*tx_byte_func)(unsigned char byte);
+
+enum board_type {
+ BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
+ BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
+ BOARD_TYPE_USER1, /* SV mobile */
+ BOARD_TYPE_USER2, /* SV desktop */
+ BOARD_TYPE_USER3, /* SV server */
+ BOARD_TYPE_ULT, /* ULT */
+ BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
+ BOARD_TYPE_UNKNOWN,
+};
+
+#define MAX_USB2_PORTS 14
+#define MAX_USB3_PORTS 6
+#define USB_OC_PIN_SKIP 8
+
+enum usb2_port_location {
+ USB_PORT_BACK_PANEL = 0,
+ USB_PORT_FRONT_PANEL,
+ USB_PORT_DOCK,
+ USB_PORT_MINI_PCIE,
+ USB_PORT_FLEX,
+ USB_PORT_INTERNAL,
+ USB_PORT_SKIP,
+ USB_PORT_NGFF_DEVICE_DOWN,
+};
+
+struct usb2_port_setting {
+ /*
+ * Usb Port Length:
+ * [16:4] = length in inches in octal format
+ * [3:0] = decimal point
+ */
+ uint16_t length;
+ uint8_t enable;
+ uint8_t oc_pin;
+ uint8_t location;
+} __attribute__((packed));
+
+struct usb3_port_setting {
+ uint8_t enable;
+ uint8_t oc_pin;
+ /*
+ * Set to 0 if trace length is > 5 inches
+ * Set to 1 if trace length is <= 5 inches
+ */
+ uint8_t fixed_eq;
+} __attribute__((packed));
+
+struct pei_data
+{
+ uint32_t pei_version;
+
+ enum board_type board_type;
+ int boot_mode;
+ int ec_present;
+ int usbdebug;
+
+ /* Base addresses */
+ uint32_t pciexbar;
+ uint16_t smbusbar;
+ uint32_t xhcibar;
+ uint32_t ehcibar;
+ uint32_t gttbar;
+ uint32_t rcba;
+ uint32_t pmbase;
+ uint32_t gpiobase;
+ uint32_t temp_mmio_base;
+ uint32_t tseg_size;
+
+ /*
+ * 0 = leave channel enabled
+ * 1 = disable dimm 0 on channel
+ * 2 = disable dimm 1 on channel
+ * 3 = disable dimm 0+1 on channel
+ */
+ int dimm_channel0_disabled;
+ int dimm_channel1_disabled;
+ /* Set to 0 for memory down */
+ uint8_t spd_addresses[4];
+ /* Enable 2x Refresh Mode */
+ int ddr_refresh_2x;
+ /* DQ pins are interleaved on board */
+ int dq_pins_interleaved;
+ /* Limit DDR3 frequency */
+ int max_ddr3_freq;
+ /* Disable self refresh */
+ int disable_self_refresh;
+ /* Disable cmd power/CKEPD */
+ int disable_cmd_pwr;
+
+ /* USB port configuration */
+ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
+ struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
+
+ /*
+ * USB3 board specific PHY tuning
+ */
+
+ /* Valid range: 0x69 - 0x80 */
+ uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
+ /* Valid range: 0x80 - 0x9c */
+ uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
+ /* Valid range: 0x39 - 0x80 */
+ uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
+ /* Valid range: 0x3d - 0x4a */
+ uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
+
+ /* Console output function */
+ tx_byte_func tx_byte;
+
+ /*
+ * DIMM SPD data for memory down configurations
+ * [CHANNEL][SLOT][SPD]
+ */
+ uint8_t spd_data[2][2][512];
+
+ /*
+ * LPDDR3 DQ byte map
+ * [CHANNEL][ITERATION][2]
+ *
+ * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
+ * DQByteMap[0] - ClkDQByteMap:
+ * - If clock is per rank, program to [0xFF, 0xFF]
+ * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+ * - If clock is shared by 2 ranks but does not go to all bytes,
+ * Entry[i] defines which DQ bytes Group i services
+ * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
+ * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
+ * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
+ * For DDR, DQByteMap[3:1] = [0xFF, 0]
+ * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
+ * since we have 1 CTL / rank
+ * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
+ * since we have 1 CA Vref
+ */
+ uint8_t dq_map[2][6][2];
+
+ /*
+ * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
+ * [CHANNEL][MAX_BYTES]
+ */
+ uint8_t dqs_map[2][8];
+
+ /* Data read from flash and passed into MRC */
+ const void *saved_data;
+ int saved_data_size;
+
+ /* Disable use of saved data (can be set by mainboard) */
+ int disable_saved_data;
+
+ /* Data from MRC that should be saved to flash */
+ void *data_to_save;
+ int data_to_save_size;
+ struct memory_info meminfo;
+} __attribute__((packed));
+
+typedef struct pei_data PEI_DATA;
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
new file mode 100644
index 0000000..3ade4ff
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_PEI_WRAPPER_H_
+#define _BROADWELL_PEI_WRAPPER_H_
+
+#include <soc/pei_data.h>
+
+typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
+
+static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
+ uint16_t length, uint8_t enable,
+ uint8_t oc_pin, uint8_t location)
+{
+ pei_data->usb2_ports[port].length = length;
+ pei_data->usb2_ports[port].enable = enable;
+ pei_data->usb2_ports[port].oc_pin = oc_pin;
+ pei_data->usb2_ports[port].location = location;
+}
+
+static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
+ uint8_t enable, uint8_t oc_pin,
+ uint8_t fixed_eq)
+{
+ pei_data->usb3_ports[port].enable = enable;
+ pei_data->usb3_ports[port].oc_pin = oc_pin;
+ pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data);
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h
new file mode 100644
index 0000000..6bc98ef
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/pm.h
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_PM_H_
+#define _BROADWELL_PM_H_
+
+/* ACPI_BASE_ADDRESS / PMBASE */
+
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define BM_STS (1 << 4)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP (7 << 10)
+#define SLP_TYP_SHIFT 10
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define SMI_EN 0x30
+#define XHCI_SMI_EN (1 << 31)
+#define ME_SMI_EN (1 << 30)
+#define GPIO_UNLOCK_SMI_EN (1 << 27)
+#define INTEL_USB2_EN (1 << 18)
+#define LEGACY_USB2_EN (1 << 17)
+#define PERIODIC_EN (1 << 14)
+#define TCO_EN (1 << 13)
+#define MCSMI_EN (1 << 11)
+#define BIOS_RLS (1 << 7)
+#define SWSMI_TMR_EN (1 << 6)
+#define APMC_EN (1 << 5)
+#define SLP_SMI_EN (1 << 4)
+#define LEGACY_USB_EN (1 << 3)
+#define BIOS_EN (1 << 2)
+#define EOS (1 << 1)
+#define GBL_SMI_EN (1 << 0)
+#define SMI_STS 0x34
+#define UPWRC 0x3c
+#define UPWRC_WS (1 << 8)
+#define UPWRC_WE (1 << 1)
+#define UPWRC_SMI (1 << 0)
+#define GPE_CNTL 0x42
+#define SWGPE_CTRL (1 << 1)
+#define DEVACT_STS 0x44
+#define PM2_CNT 0x50
+#define TCO1_CNT 0x60
+#define TCO_TMR_HLT (1 << 11)
+#define TCO1_STS 0x64
+#define DMISCI_STS (1 << 9)
+#define TCO2_STS 0x66
+#define TCO2_STS_SECOND_TO (1 << 1)
+
+#define GPE0_STS(x) (0x80 + (x * 4))
+#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
+#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
+#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
+#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
+#define WADT_STS (1 << 18)
+#define GP27_STS (1 << 16)
+#define PME_B0_STS (1 << 13)
+#define ME_SCI_STS (1 << 12)
+#define PME_STS (1 << 11)
+#define BATLOW_STS (1 << 10)
+#define PCI_EXP_STS (1 << 9)
+#define SMB_WAK_STS (1 << 7)
+#define TCOSCI_STS (1 << 6)
+#define SWGPE_STS (1 << 2)
+#define HOT_PLUG_STS (1 << 1)
+#define GPE0_EN(x) (0x90 + (x * 4))
+#define WADT_en (1 << 18)
+#define GP27_EN (1 << 16)
+#define PME_B0_EN (1 << 13)
+#define ME_SCI_EN (1 << 12)
+#define PME_EN (1 << 11)
+#define BATLOW_EN (1 << 10)
+#define PCI_EXP_EN (1 << 9)
+#define TCOSCI_EN (1 << 6)
+#define SWGPE_EN (1 << 2)
+#define HOT_PLUG_EN (1 << 1)
+
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
+#define MAINBOARD_POWER_KEEP 2
+
+#define SLEEP_STATE_S0 0
+#define SLEEP_STATE_S3 3
+#define SLEEP_STATE_S5 5
+
+struct chipset_power_state {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t pm1_cnt;
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
+ uint32_t gpe0_sts[4];
+ uint32_t gpe0_en[4];
+ uint16_t gen_pmcon1;
+ uint16_t gen_pmcon2;
+ uint16_t gen_pmcon3;
+ int prev_sleep_state;
+ uint16_t hsio_version;
+ uint16_t hsio_checksum;
+};
+
+/* PM1_CNT */
+void enable_pm1_control(uint32_t mask);
+void disable_pm1_control(uint32_t mask);
+
+/* PM1 */
+uint16_t clear_pm1_status(void);
+void enable_pm1(uint16_t events);
+uint32_t clear_smi_status(void);
+
+/* SMI */
+void enable_smi(uint32_t mask);
+void disable_smi(uint32_t mask);
+
+/* ALT_GP_SMI */
+uint32_t clear_alt_smi_status(void);
+void enable_alt_smi(uint32_t mask);
+
+/* TCO */
+uint32_t clear_tco_status(void);
+void enable_tco_sci(void);
+
+/* GPE0 */
+uint32_t clear_gpe_status(void);
+void clear_gpe_enable(void);
+void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4);
+void disable_all_gpe(void);
+void enable_gpe(uint32_t mask);
+void disable_gpe(uint32_t mask);
+
+/* Return the selected ACPI SCI IRQ */
+int acpi_sci_irq(void);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h
new file mode 100644
index 0000000..9242aa9
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/ramstage.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_RAMSTAGE_H_
+#define _BROADWELL_RAMSTAGE_H_
+
+#include <device/device.h>
+#include <soc/intel/broadwell/chip.h>
+
+void broadwell_init_pre_device(void *chip_info);
+void broadwell_init_cpus(device_t dev);
+void broadwell_pch_enable_dev(device_t dev);
+
+#if CONFIG_HAVE_REFCODE_BLOB
+void broadwell_run_reference_code(void);
+#else
+static inline void broadwell_run_reference_code(void) { }
+#endif
+
+extern struct pci_operations broadwell_pci_ops;
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/rcba.h b/src/soc/intel/broadwell/include/soc/rcba.h
new file mode 100644
index 0000000..2c40d07
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/rcba.h
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_RCBA_H_
+#define _BROADWELL_RCBA_H_
+
+#include <soc/iomap.h>
+
+#define RCBA8(x) *((volatile u8 *)(RCBA_BASE_ADDRESS + x))
+#define RCBA16(x) *((volatile u16 *)(RCBA_BASE_ADDRESS + x))
+#define RCBA32(x) *((volatile u32 *)(RCBA_BASE_ADDRESS + x))
+
+#define RCBA_AND_OR(bits, x, and, or) \
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+
+#define RPC 0x0400 /* 32bit */
+#define RPFN 0x0404 /* 32bit */
+
+/* Root Port configuration space hide */
+#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
+/* Get the function number assigned to a Root Port */
+#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
+/* Set the function number for a Root Port */
+#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
+/* Root Port function number mask */
+#define RPFN_FNMASK(port) (7 << ((port) * 4))
+
+#define NOINT 0
+#define INTA 1
+#define INTB 2
+#define INTC 3
+#define INTD 4
+
+#define DIR_IDR 12 /* Interrupt D Pin Offset */
+#define DIR_ICR 8 /* Interrupt C Pin Offset */
+#define DIR_IBR 4 /* Interrupt B Pin Offset */
+#define DIR_IAR 0 /* Interrupt A Pin Offset */
+
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+/* IO Buffer Programming */
+#define IOBPIRI 0x2330
+#define IOBPD 0x2334
+#define IOBPS 0x2338
+#define IOBPS_READY 0x0001
+#define IOBPS_TX_MASK 0x0006
+#define IOBPS_MASK 0xff00
+#define IOBPS_READ 0x0600
+#define IOBPS_WRITE 0x0700
+#define IOBPU 0x233a
+#define IOBPU_MAGIC 0xf000
+#define IOBP_PCICFG_READ 0x0400
+#define IOBP_PCICFG_WRITE 0x0500
+
+#define D31IP 0x3100 /* 32bit */
+#define D31IP_TTIP 24 /* Thermal Throttle Pin */
+#define D31IP_SIP2 20 /* SATA Pin 2 */
+#define D31IP_SMIP 12 /* SMBUS Pin */
+#define D31IP_SIP 8 /* SATA Pin */
+#define D30IP 0x3104 /* 32bit */
+#define D30IP_PIP 0 /* PCI Bridge Pin */
+#define D29IP 0x3108 /* 32bit */
+#define D29IP_E1P 0 /* EHCI #1 Pin */
+#define D28IP 0x310c /* 32bit */
+#define D28IP_P8IP 28 /* PCI Express Port 8 */
+#define D28IP_P7IP 24 /* PCI Express Port 7 */
+#define D28IP_P6IP 20 /* PCI Express Port 6 */
+#define D28IP_P5IP 16 /* PCI Express Port 5 */
+#define D28IP_P4IP 12 /* PCI Express Port 4 */
+#define D28IP_P3IP 8 /* PCI Express Port 3 */
+#define D28IP_P2IP 4 /* PCI Express Port 2 */
+#define D28IP_P1IP 0 /* PCI Express Port 1 */
+#define D27IP 0x3110 /* 32bit */
+#define D27IP_ZIP 0 /* HD Audio Pin */
+#define D26IP 0x3114 /* 32bit */
+#define D26IP_E2P 0 /* EHCI #2 Pin */
+#define D25IP 0x3118 /* 32bit */
+#define D25IP_LIP 0 /* GbE LAN Pin */
+#define D22IP 0x3124 /* 32bit */
+#define D22IP_KTIP 12 /* KT Pin */
+#define D22IP_IDERIP 8 /* IDE-R Pin */
+#define D22IP_MEI2IP 4 /* MEI #2 Pin */
+#define D22IP_MEI1IP 0 /* MEI #1 Pin */
+#define D20IP 0x3128 /* 32bit */
+#define D20IP_XHCI 0 /* XHCI Pin */
+#define D31IR 0x3140 /* 16bit */
+#define D30IR 0x3142 /* 16bit */
+#define D29IR 0x3144 /* 16bit */
+#define D28IR 0x3146 /* 16bit */
+#define D27IR 0x3148 /* 16bit */
+#define D26IR 0x314c /* 16bit */
+#define D25IR 0x3150 /* 16bit */
+#define D23IR 0x3158 /* 16bit */
+#define D22IR 0x315c /* 16bit */
+#define D20IR 0x3160 /* 16bit */
+#define D21IR 0x3164 /* 16bit */
+#define D19IR 0x3168 /* 16bit */
+#define ACPIIRQEN 0x31e0 /* 32bit */
+#define OIC 0x31fe /* 16bit */
+#define DEEP_S3_POL 0x3328 /* 32bit */
+#define DEEP_S3_EN_AC (1 << 0)
+#define DEEP_S3_EN_DC (1 << 1)
+#define DEEP_S5_POL 0x3330 /* 32bit */
+#define DEEP_S5_EN_AC (1 << 14)
+#define DEEP_S5_EN_DC (1 << 15)
+#define DEEP_SX_CONFIG 0x3334 /* 32bit */
+#define DEEP_SX_WAKE_PIN_EN (1 << 2)
+#define DEEP_SX_ACPRESENT_PD (1 << 1)
+#define DEEP_SX_GP27_PIN_EN (1 << 0)
+#define PMSYNC_CONFIG 0x33c4 /* 32bit */
+#define PMSYNC_CONFIG2 0x33cc /* 32bit */
+#define SOFT_RESET_CTRL 0x38f4
+#define SOFT_RESET_DATA 0x38f8
+
+#define DIR_ROUTE(a,b,c,d) \
+ (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define RC 0x3400 /* 32bit */
+#define HPTC 0x3404 /* 32bit */
+#define GCS 0x3410 /* 32bit */
+#define BUC 0x3414 /* 32bit */
+#define PCH_DISABLE_GBE (1 << 5)
+#define FD 0x3418 /* 32bit */
+#define FDSW 0x3420 /* 8bit */
+#define DISPBDF 0x3424 /* 16bit */
+#define FD2 0x3428 /* 32bit */
+#define CG 0x341c /* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS (1 << 0)
+#define PCH_DISABLE_ADSPD (1 << 1)
+#define PCH_DISABLE_SATA1 (1 << 2)
+#define PCH_DISABLE_SMBUS (1 << 3)
+#define PCH_DISABLE_HD_AUDIO (1 << 4)
+#define PCH_DISABLE_EHCI2 (1 << 13)
+#define PCH_DISABLE_LPC (1 << 14)
+#define PCH_DISABLE_EHCI1 (1 << 15)
+#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
+#define PCH_DISABLE_THERMAL (1 << 24)
+#define PCH_DISABLE_SATA2 (1 << 25)
+#define PCH_DISABLE_XHCI (1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT (1 << 4)
+#define PCH_DISABLE_IDER (1 << 3)
+#define PCH_DISABLE_MEI2 (1 << 2)
+#define PCH_DISABLE_MEI1 (1 << 1)
+#define PCH_ENABLE_DBDF (1 << 0)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/reset.h b/src/soc/intel/broadwell/include/soc/reset.h
new file mode 100644
index 0000000..6f21181
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/reset.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_RESET_H_
+#define _BROADWELL_RESET_H_
+
+void reset_system(void);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
new file mode 100644
index 0000000..946d1d0
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_ROMSTAGE_H_
+#define _BROADWELL_ROMSTAGE_H_
+
+#include <stdint.h>
+#include <arch/cpu.h>
+
+struct chipset_power_state;
+struct pei_data;
+struct romstage_params {
+ unsigned long bist;
+ struct chipset_power_state *power_state;
+ struct pei_data *pei_data;
+};
+
+void mainboard_romstage_entry(struct romstage_params *params);
+void romstage_common(struct romstage_params *params);
+void *asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo,
+ uint32_t tsc_high);
+void asmlinkage romstage_after_car(void);
+void raminit(struct pei_data *pei_data);
+void *setup_stack_and_mttrs(void);
+
+struct chipset_power_state;
+struct chipset_power_state *fill_power_state(void);
+void report_platform_info(void);
+void report_memory_config(void);
+
+void set_max_freq(void);
+
+void systemagent_early_init(void);
+void pch_early_init(void);
+void pch_uart_init(void);
+void intel_early_me_status(void);
+
+void enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
+
+int early_spi_read(u32 offset, u32 size, u8 *buffer);
+int early_spi_read_wpsr(u8 *sr);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/soc/intel/broadwell/include/soc/sata.h
new file mode 100644
index 0000000..357fe58
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/sata.h
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_SATA_H_
+#define _BROADWELL_SATA_H_
+
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
+#define SATA_SP 0xd0 /* Scratchpad */
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+#define SATA_IOBP_SP0DTLE_DATA 0xea002550
+#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
+#define SATA_IOBP_SP1DTLE_DATA 0xea002750
+#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
+
+#define SATA_DTLE_MASK 0xF
+#define SATA_DTLE_DATA_SHIFT 24
+#define SATA_DTLE_EDGE_SHIFT 16
+
+/* PCI Configuration Space (D31:F1): IDE */
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
+#define IDE_DECODE_ENABLE (1 << 15)
+#define IDE_SITRE (1 << 14)
+#define IDE_ISP_5_CLOCKS (0 << 12)
+#define IDE_ISP_4_CLOCKS (1 << 12)
+#define IDE_ISP_3_CLOCKS (2 << 12)
+#define IDE_RCT_4_CLOCKS (0 << 8)
+#define IDE_RCT_3_CLOCKS (1 << 8)
+#define IDE_RCT_2_CLOCKS (2 << 8)
+#define IDE_RCT_1_CLOCKS (3 << 8)
+#define IDE_DTE1 (1 << 7)
+#define IDE_PPE1 (1 << 6)
+#define IDE_IE1 (1 << 5)
+#define IDE_TIME1 (1 << 4)
+#define IDE_DTE0 (1 << 3)
+#define IDE_PPE0 (1 << 2)
+#define IDE_IE0 (1 << 1)
+#define IDE_TIME0 (1 << 0)
+#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
+
+#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
+#define IDE_SSDE1 (1 << 3)
+#define IDE_SSDE0 (1 << 2)
+#define IDE_PSDE1 (1 << 1)
+#define IDE_PSDE0 (1 << 0)
+
+#define IDE_SDMA_TIM 0x4a
+
+#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
+#define SIG_MODE_SEC_NORMAL (0 << 18)
+#define SIG_MODE_SEC_TRISTATE (1 << 18)
+#define SIG_MODE_SEC_DRIVELOW (2 << 18)
+#define SIG_MODE_PRI_NORMAL (0 << 16)
+#define SIG_MODE_PRI_TRISTATE (1 << 16)
+#define SIG_MODE_PRI_DRIVELOW (2 << 16)
+#define FAST_SCB1 (1 << 15)
+#define FAST_SCB0 (1 << 14)
+#define FAST_PCB1 (1 << 13)
+#define FAST_PCB0 (1 << 12)
+#define SCB1 (1 << 3)
+#define SCB0 (1 << 2)
+#define PCB1 (1 << 1)
+#define PCB0 (1 << 0)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/serialio.h b/src/soc/intel/broadwell/include/soc/serialio.h
new file mode 100644
index 0000000..2fd6dca
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/serialio.h
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_SERIALIO_H_
+#define _BROADWELL_SERIALIO_H_
+
+/* Serial IO IOBP Registers */
+#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
+#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5)
+#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4)
+#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
+#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
+#define SIO_IOBP_GPIODF 0xcb000154
+#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4)
+#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3)
+#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2)
+#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1)
+#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0)
+#define SIO_IOBP_GPIODF_UART0_BYTE_ACCESS (1 << 10)
+#define SIO_IOBP_GPIODF_UART1_BYTE_ACCESS (1 << 11)
+#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
+#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
+#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
+#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */
+#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */
+#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */
+#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
+#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
+/* PORTCTRL 2-8 have the same layout */
+#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21)
+#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20)
+#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
+#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
+#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1)
+#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
+#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
+#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
+#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */
+#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */
+#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
+#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
+#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
+#define SIO_IOBP_FUNCDIS_DIS (1 << 8)
+
+/* Serial IO Devices */
+#define SIO_ID_SDMA 0 /* D21:F0 */
+#define SIO_ID_I2C0 1 /* D21:F1 */
+#define SIO_ID_I2C1 2 /* D21:F2 */
+#define SIO_ID_SPI0 3 /* D21:F3 */
+#define SIO_ID_SPI1 4 /* D21:F4 */
+#define SIO_ID_UART0 5 /* D21:F5 */
+#define SIO_ID_UART1 6 /* D21:F6 */
+#define SIO_ID_SDIO 7 /* D23:F0 */
+
+#define SIO_REG_PPR_CLOCK 0x800
+#define SIO_REG_PPR_CLOCK_EN (1 << 0)
+#define SIO_REG_PPR_CLOCK_UPDATE (1 << 31)
+#define SIO_REG_PPR_CLOCK_M_DIV 0x25a
+#define SIO_REG_PPR_CLOCK_N_DIV 0x7fff
+#define SIO_REG_PPR_RST 0x804
+#define SIO_REG_PPR_RST_ASSERT 0x3
+#define SIO_REG_PPR_GEN 0x808
+#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2)
+#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3)
+#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
+#define SIO_REG_AUTO_LTR 0x814
+
+#define SIO_REG_SDIO_PPR_GEN 0x1008
+#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
+#define SIO_REG_SDIO_PPR_CMD12 0x3c
+#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30)
+
+#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
+#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
+#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
+#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/smbus.h b/src/soc/intel/broadwell/include/soc/smbus.h
new file mode 100644
index 0000000..fb13c2d
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/smbus.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu at gmail.com>
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_SMBUS_H_
+#define _BROADWELL_SMBUS_H_
+
+/* PCI Configuration Space (D31:F3): SMBus */
+#define SMB_BASE 0x20
+#define HOSTC 0x40
+#define HST_EN (1 << 0)
+#define SMB_RCV_SLVA 0x09
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT 0x0
+#define SMBHSTCTL 0x2
+#define SMBHSTCMD 0x3
+#define SMBXMITADD 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBBLKDAT 0x7
+#define SMBTRNSADD 0x9
+#define SMBSLVDATA 0xa
+#define SMLINK_PIN_CTL 0xe
+#define SMBUS_PIN_CTL 0xf
+
+#define SMBUS_TIMEOUT (10 * 1000 * 100)
+#define SMBUS_SLAVE_ADDR 0x24
+
+int do_smbus_read_byte(unsigned smbus_base, unsigned device,
+ unsigned address);
+int do_smbus_write_byte(unsigned smbus_base, unsigned device,
+ unsigned address, unsigned data);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/smm.h b/src/soc/intel/broadwell/include/soc/smm.h
new file mode 100644
index 0000000..f7f515c
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/smm.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_SMM_H_
+#define _BROADWELL_SMM_H_
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+
+struct ied_header {
+ char signature[10];
+ u32 size;
+ u8 reserved[34];
+} __attribute__ ((packed));
+
+struct smm_relocation_params {
+ u32 smram_base;
+ u32 smram_size;
+ u32 ied_base;
+ u32 ied_size;
+ msr_t smrr_base;
+ msr_t smrr_mask;
+ msr_t emrr_base;
+ msr_t emrr_mask;
+ msr_t uncore_emrr_base;
+ msr_t uncore_emrr_mask;
+ /* The smm_save_state_in_msrs field indicates if SMM save state
+ * locations live in MSRs. This indicates to the CPUs how to adjust
+ * the SMMBASE and IEDBASE */
+ int smm_save_state_in_msrs;
+};
+
+/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig
+ * is included after chipset code. This causes the chipset's Kconfig to be
+ * clobbered by the arch/x86/Kconfig if they have the same name. */
+static inline int smm_region_size(void)
+{
+ /* Make it 8MiB by default. */
+ if (CONFIG_SMM_TSEG_SIZE == 0)
+ return (8 << 20);
+ return CONFIG_SMM_TSEG_SIZE;
+}
+
+int smm_initialize(void);
+void smm_relocate(void);
+
+/* These helpers are for performing SMM relocation. */
+void southbridge_trigger_smi(void);
+void southbridge_clear_smi_status(void);
+
+/* The initialization of the southbridge is split into 2 components. One is
+ * for clearing the state in the SMM registers. The other is for enabling
+ * SMIs. They are split so that other work between the 2 actions. */
+void southbridge_smm_clear_state(void);
+void southbridge_smm_enable_smi(void);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/spi.h b/src/soc/intel/broadwell/include/soc/spi.h
new file mode 100644
index 0000000..8b95f70
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/spi.h
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_SPI_H_
+#define _BROADWELL_SPI_H_
+
+/*
+ * SPI Opcode Menu setup for SPIBAR lockdown
+ * should support most common flash chips.
+ */
+
+#define SPIBAR_OFFSET 0x3800
+#define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET)
+#define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET)
+#define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET)
+
+/* Registers within the SPIBAR */
+#define SPIBAR_SSFC 0x91
+#define SPIBAR_FDOC 0xb0
+#define SPIBAR_FDOD 0xb4
+
+#define SPIBAR_PREOP 0x94
+#define SPIBAR_OPTYPE 0x96
+#define SPIBAR_OPMENU_LOWER 0x98
+#define SPIBAR_OPMENU_UPPER 0x9c
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+ (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+ (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
+#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
+#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
+#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
+#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
+#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
+#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
+#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
+#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
+#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
+#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
+#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
+#define SPIBAR_FADDR 0x08 /* SPI flash address */
+#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
+#define SPIBAR_SSFS 0x90
+#define SPIBAR_SSFS_ERROR (1 << 3)
+#define SPIBAR_SSFS_DONE (1 << 2)
+#define SPIBAR_SSFC 0x91
+#define SPIBAR_SSFC_DATA (1 << 14)
+#define SPIBAR_SSFC_GO (1 << 1)
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/systemagent.h b/src/soc/intel/broadwell/include/soc/systemagent.h
new file mode 100644
index 0000000..5142b09
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/systemagent.h
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_SYSTEMAGENT_H_
+#define _BROADWELL_SYSTEMAGENT_H_
+
+#include <soc/iomap.h>
+
+#define SA_IGD_OPROM_VENDEV 0x80860406
+
+#define IGD_HASWELL_ULT_GT1 0x0a06
+#define IGD_HASWELL_ULT_GT2 0x0a16
+#define IGD_HASWELL_ULT_GT3 0x0a26
+#define IGD_BROADWELL_U_GT1 0x1606
+#define IGD_BROADWELL_U_GT2 0x1616
+#define IGD_BROADWELL_U_GT3_15W 0x1626
+#define IGD_BROADWELL_U_GT3_28W 0x162b
+#define IGD_BROADWELL_Y_GT2 0x161e
+#define IGD_BROADWELL_H_GT2 0x1612
+#define IGD_BROADWELL_H_GT3 0x1622
+
+#define MCH_BROADWELL_ID_U_Y 0x1604
+#define MCH_BROADWELL_REV_D0 0x06
+#define MCH_BROADWELL_REV_E0 0x08
+#define MCH_BROADWELL_REV_F0 0x09
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR 0x40
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define DMIBAR 0x68
+#define GGC 0x50 /* GMCH Graphics Control */
+#define DEVEN 0x54 /* Device Enable */
+#define DEVEN_D7EN (1 << 14)
+#define DEVEN_D4EN (1 << 7)
+#define DEVEN_D3EN (1 << 5)
+#define DEVEN_D2EN (1 << 4)
+#define DEVEN_D1F0EN (1 << 3)
+#define DEVEN_D1F1EN (1 << 2)
+#define DEVEN_D1F2EN (1 << 1)
+#define DEVEN_D0EN (1 << 0)
+#define DPR 0x5c
+#define DPR_EPM (1 << 2)
+#define DPR_PRS (1 << 1)
+#define DPR_SIZE_MASK 0xff0
+
+#define PAM0 0x80
+#define PAM1 0x81
+#define PAM2 0x82
+#define PAM3 0x83
+#define PAM4 0x84
+#define PAM5 0x85
+#define PAM6 0x86
+
+#define SMRAM 0x88 /* System Management RAM Control */
+#define D_OPEN (1 << 6)
+#define D_CLS (1 << 5)
+#define D_LCK (1 << 4)
+#define G_SMRAME (1 << 3)
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+
+#define MESEG_BASE 0x70 /* Management Engine Base. */
+#define MESEG_LIMIT 0x78 /* Management Engine Limit. */
+#define REMAPBASE 0x90 /* Remap base. */
+#define REMAPLIMIT 0x98 /* Remap limit. */
+#define TOM 0xa0 /* Top of DRAM in memory controller space. */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define SKPAD 0xdc /* Scratchpad Data */
+
+/* MCHBAR */
+
+#define MCHBAR8(x) *((volatile u8 *)(MCH_BASE_ADDRESS + x))
+#define MCHBAR16(x) *((volatile u16 *)(MCH_BASE_ADDRESS + x))
+#define MCHBAR32(x) *((volatile u32 *)(MCH_BASE_ADDRESS + x))
+
+#define MCHBAR_PEI_VERSION 0x5034
+#define BIOS_RESET_CPL 0x5da8
+#define EDRAMBAR 0x5408
+#define MCH_PAIR 0x5418
+#define GDXCBAR 0x5420
+
+#define MCH_PKG_POWER_LIMIT_LO 0x59a0
+#define MCH_PKG_POWER_LIMIT_HI 0x59a4
+#define MCH_DDR_POWER_LIMIT_LO 0x58e0
+#define MCH_DDR_POWER_LIMIT_HI 0x58e4
+
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE 0x5da4
+#define MAILBOX_RUN_BUSY (1 << 31)
+#define MAILBOX_BIOS_CMD_READ_PCS 1
+#define MAILBOX_BIOS_CMD_WRITE_PCS 2
+#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
+#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
+#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
+#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
+/* Errors are returned back in bits 7:0. */
+#define MAILBOX_BIOS_ERROR_NONE 0
+#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1
+#define MAILBOX_BIOS_ERROR_TIMEOUT 2
+#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3
+#define MAILBOX_BIOS_ERROR_RESERVED 4
+#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5
+#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6
+#define MAILBOX_BIOS_ERROR_VR_ERROR 7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA 0x5da0
+
+/* System Agent identification */
+u8 systemagent_revision(void);
+
+#endif
diff --git a/src/soc/intel/broadwell/include/soc/xhci.h b/src/soc/intel/broadwell/include/soc/xhci.h
new file mode 100644
index 0000000..3f4fb4e
--- /dev/null
+++ b/src/soc/intel/broadwell/include/soc/xhci.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BROADWELL_XHCI_H_
+#define _BROADWELL_XHCI_H_
+
+/* XHCI PCI Registers */
+#define XHCI_PWR_CTL_STS 0x74
+#define XHCI_PWR_CTL_SET_MASK 0x3
+#define XHCI_PWR_CTL_SET_D0 0x0
+#define XHCI_PWR_CTL_SET_D3 0x3
+#define XHCI_PWR_CTL_ENABLE_PME (1 << 8)
+#define XHCI_PWR_CTL_STATUS_PME (1 << 15)
+#define XHCI_USB2PR 0xd0
+#define XHCI_USB2PRM 0xd4
+#define XHCI_USB2PR_HCSEL 0x7fff
+#define XHCI_USB3PR 0xd8
+#define XHCI_USB3PR_SSEN 0x3f
+#define XHCI_USB3PRM 0xdc
+#define XHCI_USB3FUS 0xe0
+#define XHCI_USB3FUS_SS_MASK 3
+#define XHCI_USB3FUS_SS_SHIFT 3
+#define XHCI_USB3PDO 0xe8
+
+/* XHCI Memory Registers */
+#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10))
+#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
+#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
+#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */
+#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
+#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
+#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
+#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
+#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
+#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
+#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */
+#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */
+#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */
+#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */
+
+#ifdef __SMM__
+void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ);
+#endif
+
+#endif
diff --git a/src/soc/intel/broadwell/iobp.c b/src/soc/intel/broadwell/iobp.c
index a0b850e..870f6af 100644
--- a/src/soc/intel/broadwell/iobp.c
+++ b/src/soc/intel/broadwell/iobp.c
@@ -20,8 +20,8 @@
#include <console/console.h>
#include <delay.h>
#include <arch/io.h>
-#include <broadwell/iobp.h>
-#include <broadwell/rcba.h>
+#include <soc/iobp.h>
+#include <soc/rcba.h>
#define IOBP_RETRY 1000
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 5efcb73..6ebc758 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -34,17 +34,17 @@
#include <cbmem.h>
#include <reg_script.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iobp.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
+#include <soc/gpio.h>
+#include <soc/iobp.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 2a0ce66..c2bbb49 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -35,13 +35,13 @@
#include <string.h>
#include <delay.h>
#include <elog.h>
-#include <broadwell/me.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
+#include <soc/me.h>
+#include <soc/lpc.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c
index 033e4e2..867a9a9 100644
--- a/src/soc/intel/broadwell/me_status.c
+++ b/src/soc/intel/broadwell/me_status.c
@@ -23,8 +23,8 @@
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/me.h>
+#include <soc/pci_devs.h>
+#include <soc/me.h>
#include <delay.h>
static inline void me_read_dword_ptr(void *ptr, int offset)
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 28f4062..7b8df28 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -20,8 +20,8 @@
#include <arch/io.h>
#include <cbmem.h>
#include <device/pci.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/systemagent.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
static uintptr_t dpr_region_start(void)
{
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 6fd8e63..ac5af8d 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -28,7 +28,7 @@
#include <delay.h>
#include <stdlib.h>
#include <soc/intel/common/hda_verb.h>
-#include <broadwell/ramstage.h>
+#include <soc/ramstage.h>
static const u32 minihd_verb_table[] = {
/* coreboot specific header */
diff --git a/src/soc/intel/broadwell/monotonic_timer.c b/src/soc/intel/broadwell/monotonic_timer.c
index ace9e60..39134ef 100644
--- a/src/soc/intel/broadwell/monotonic_timer.c
+++ b/src/soc/intel/broadwell/monotonic_timer.c
@@ -20,7 +20,7 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <timer.h>
-#include <broadwell/msr.h>
+#include <soc/msr.h>
static struct monotonic_counter {
int initialized;
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index 492d177..54c5567 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -24,13 +24,13 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
-#include <broadwell/iobp.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/serialio.h>
-#include <broadwell/spi.h>
+#include <soc/iobp.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/serialio.h>
+#include <soc/spi.h>
u8 pch_revision(void)
{
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index 10b6230..c1aa910 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -24,14 +24,14 @@
#include <device/pciexp.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#include <broadwell/gpio.h>
-#include <broadwell/lpc.h>
-#include <broadwell/iobp.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
-#include <broadwell/cpu.h>
+#include <soc/gpio.h>
+#include <soc/lpc.h>
+#include <soc/iobp.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
+#include <soc/cpu.h>
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index 9ae7268..b87202f 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -20,10 +20,10 @@
#include <stdlib.h>
#include <stdint.h>
#include <console/streams.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/smm.h>
+#include <soc/iomap.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/smm.h>
static void ABI_X86 send_to_console(unsigned char b)
{
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 272731c..7686387 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -27,11 +27,11 @@
#include <device/pci.h>
#include <device/pci_def.h>
#include <console/console.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/gpio.h>
/* Print status bits with descriptive names */
static void print_status_bits(u32 status, const char *bit_names[])
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index 2097f2f..beabded 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -23,10 +23,10 @@
#include <device/device.h>
#include <stdlib.h>
#include <string.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pm.h>
-#include <broadwell/ramstage.h>
-#include <chip.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/ramstage.h>
+#include <soc/intel/broadwell/chip.h>
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index 36ce97d..b7962f1 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -30,9 +30,9 @@
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/vboot_handoff.h>
#endif
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/ramstage.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/ramstage.h>
static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
{
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
index 5117b29..a56ec24 100644
--- a/src/soc/intel/broadwell/reset.c
+++ b/src/soc/intel/broadwell/reset.c
@@ -21,7 +21,7 @@
#include <arch/io.h>
#include <halt.h>
#include <reset.h>
-#include <broadwell/reset.h>
+#include <soc/reset.h>
/*
* Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c
index 754bc31..af175be 100644
--- a/src/soc/intel/broadwell/romstage/cpu.c
+++ b/src/soc/intel/broadwell/romstage/cpu.c
@@ -21,9 +21,9 @@
#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/romstage.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/romstage.h>
u32 cpu_family_model(void)
{
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index d064fc0..f31e6ba 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -22,15 +22,15 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <reg_script.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/rcba.h>
-#include <broadwell/romstage.h>
-#include <broadwell/smbus.h>
-#include <chip.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/rcba.h>
+#include <soc/romstage.h>
+#include <soc/smbus.h>
+#include <soc/intel/broadwell/chip.h>
const struct reg_script pch_early_init_script[] = {
/* Setup southbridge BARs */
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index 7aa6177..bdb3da9 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -28,11 +28,11 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/romstage.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
static struct chipset_power_state power_state CAR_GLOBAL;
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index ce8f879..1f62fd0 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -31,14 +31,14 @@
#endif
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/intel/common/mrc_cache.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/pm.h>
-#include <broadwell/reset.h>
-#include <broadwell/romstage.h>
-#include <broadwell/smm.h>
-#include <broadwell/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
/*
* Find PEI executable in coreboot filesystem and execute it.
diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c
index 84273e4..713b3e7 100644
--- a/src/soc/intel/broadwell/romstage/report_platform.c
+++ b/src/soc/intel/broadwell/romstage/report_platform.c
@@ -23,11 +23,11 @@
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/msr.h>
-#include <broadwell/cpu.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/romstage.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
static struct {
u32 cpuid;
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index ff5918a..31d4f88 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -31,12 +31,12 @@
#include <ramstage_cache.h>
#include <romstage_handoff.h>
#include <timestamp.h>
-#include <broadwell/me.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pm.h>
-#include <broadwell/reset.h>
-#include <broadwell/romstage.h>
-#include <broadwell/spi.h>
+#include <soc/me.h>
+#include <soc/pei_data.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
/* Entry from cache-as-ram.inc. */
void * asmlinkage romstage_main(unsigned long bist,
diff --git a/src/soc/intel/broadwell/romstage/smbus.c b/src/soc/intel/broadwell/romstage/smbus.c
index 8b3cde3..f09459b 100644
--- a/src/soc/intel/broadwell/romstage/smbus.c
+++ b/src/soc/intel/broadwell/romstage/smbus.c
@@ -23,10 +23,10 @@
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <reg_script.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/smbus.h>
-#include <broadwell/romstage.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/smbus.h>
+#include <soc/romstage.h>
static const struct reg_script smbus_init_script[] = {
/* Set SMBUS I/O base address */
diff --git a/src/soc/intel/broadwell/romstage/spi.c b/src/soc/intel/broadwell/romstage/spi.c
index 75df2fd..a2c5d33 100644
--- a/src/soc/intel/broadwell/romstage/spi.c
+++ b/src/soc/intel/broadwell/romstage/spi.c
@@ -22,9 +22,9 @@
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <delay.h>
-#include <broadwell/spi.h>
-#include <broadwell/rcba.h>
-#include <broadwell/romstage.h>
+#include <soc/spi.h>
+#include <soc/rcba.h>
+#include <soc/romstage.h>
#define SPI_DELAY 10 /* 10us */
#define SPI_RETRY 200000 /* 2s */
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index 7f56629..a81eb07 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -24,7 +24,7 @@
#include <console/console.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
-#include <broadwell/romstage.h>
+#include <soc/romstage.h>
static inline uint32_t *stack_push(u32 *stack, u32 value)
{
diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c
index 8e4d82c..7a43917 100644
--- a/src/soc/intel/broadwell/romstage/systemagent.c
+++ b/src/soc/intel/broadwell/romstage/systemagent.c
@@ -22,10 +22,10 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <reg_script.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/romstage.h>
-#include <broadwell/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
static const struct reg_script systemagent_early_init_script[] = {
REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index 8214a8a..96c9634 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -24,8 +24,8 @@
#include <reg_script.h>
#include <stdint.h>
#include <uart8250.h>
-#include <broadwell/iobp.h>
-#include <broadwell/serialio.h>
+#include <soc/iobp.h>
+#include <soc/serialio.h>
const struct reg_script uart_init[] = {
/* Set MMIO BAR */
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index 6859ffc..cfb3854 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -24,11 +24,11 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <delay.h>
-#include <broadwell/iobp.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/sata.h>
-#include <chip.h>
+#include <soc/iobp.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/sata.h>
+#include <soc/intel/broadwell/chip.h>
static inline u32 sir_read(struct device *dev, int idx)
{
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 82f37cd..6eba7ac 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -25,14 +25,14 @@
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <stdlib.h>
-#include <broadwell/iobp.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pch.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/serialio.h>
-#include <chip.h>
+#include <soc/iobp.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pch.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/serialio.h>
+#include <soc/intel/broadwell/chip.h>
/* Set D3Hot Power State in ACPI mode */
static void serialio_enable_d3hot(struct resource *res)
diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c
index a1dbdfe..0ec84b2 100644
--- a/src/soc/intel/broadwell/smbus.c
+++ b/src/soc/intel/broadwell/smbus.c
@@ -27,9 +27,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <broadwell/iomap.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/smbus.h>
+#include <soc/iomap.h>
+#include <soc/ramstage.h>
+#include <soc/smbus.h>
static void pch_smbus_init(device_t dev)
{
diff --git a/src/soc/intel/broadwell/smbus_common.c b/src/soc/intel/broadwell/smbus_common.c
index ff43dcd..41416c7 100644
--- a/src/soc/intel/broadwell/smbus_common.c
+++ b/src/soc/intel/broadwell/smbus_common.c
@@ -26,8 +26,8 @@
#include <device/smbus_def.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/smbus.h>
+#include <soc/ramstage.h>
+#include <soc/smbus.h>
static void smbus_delay(void)
{
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c
index 529346a..85a508b 100644
--- a/src/soc/intel/broadwell/smi.c
+++ b/src/soc/intel/broadwell/smi.c
@@ -26,10 +26,10 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pch.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
void southbridge_smm_clear_state(void)
{
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index e1f7e5b..5004a6a 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -29,13 +29,13 @@
#include <elog.h>
#include <halt.h>
#include <pc80/mc146818rtc.h>
-#include <broadwell/lpc.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/rcba.h>
-#include <broadwell/smm.h>
-#include <broadwell/xhci.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/rcba.h>
+#include <soc/smm.h>
+#include <soc/xhci.h>
static u8 smm_initialized = 0;
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index bd1fc26..47d6385 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -29,11 +29,11 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <console/console.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/smm.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
/* This gets filled in and used during relocation. */
static struct smm_relocation_params smm_reloc_params;
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 0069d10..6d2f103 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -28,7 +28,7 @@
#include <console/console.h>
#include <device/pci_ids.h>
#include <spi-generic.h>
-#include <broadwell/pci_devs.h>
+#include <soc/pci_devs.h>
#ifdef __SMM__
#define pci_read_config_byte(dev, reg, targ)\
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c
index 6c6b6fb..cb34297 100644
--- a/src/soc/intel/broadwell/stage_cache.c
+++ b/src/soc/intel/broadwell/stage_cache.c
@@ -19,7 +19,7 @@
#include <cbmem.h>
#include <ramstage_cache.h>
-#include <broadwell/smm.h>
+#include <soc/smm.h>
#include <stdint.h>
struct ramstage_cache *ramstage_cache_location(long *size)
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 0488ccb..d58cf21 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -30,11 +30,11 @@
#include <string.h>
#include <cbmem.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#include <broadwell/cpu.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/systemagent.h>
u8 systemagent_revision(void)
{
diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/soc/intel/broadwell/tsc_freq.c
index 80dd989..5487b16 100644
--- a/src/soc/intel/broadwell/tsc_freq.c
+++ b/src/soc/intel/broadwell/tsc_freq.c
@@ -20,8 +20,8 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
unsigned long tsc_freq_mhz(void)
{
diff --git a/src/soc/intel/broadwell/usbdebug.c b/src/soc/intel/broadwell/usbdebug.c
index d462e89..736a1a3 100644
--- a/src/soc/intel/broadwell/usbdebug.c
+++ b/src/soc/intel/broadwell/usbdebug.c
@@ -23,7 +23,7 @@
#include <usbdebug.h>
#include <device/pci.h>
#include <device/pci_def.h>
-#include <broadwell/pci_devs.h>
+#include <soc/pci_devs.h>
void set_debug_port(unsigned int port)
{
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index b330338..4c721c2 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -23,9 +23,9 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/xhci.h>
-#include <broadwell/cpu.h>
+#include <soc/ramstage.h>
+#include <soc/xhci.h>
+#include <soc/cpu.h>
#ifdef __SMM__
static u8 *usb_xhci_mem_base(device_t dev)
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