[coreboot-gerrit] Patch set updated for coreboot: 3b856ff baytrail: add code for supporting 2x ddr refresh rate
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri Apr 10 03:25:07 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9498
-gerrit
commit 3b856ff958c096c4e538141c25fa0085de9df4d4
Author: Kane Chen <kane.chen at intel.com>
Date: Sat Jan 17 08:19:54 2015 +0800
baytrail: add code for supporting 2x ddr refresh rate
this code change provides a way to enable 2x refresh rate
in RW image
In baytrail, it enables 2x refresh rate by default
BUG=chrome-os-partner:35210
BRANCH=none
TEST=check the register is set properly on rambi
Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba
Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Original-Commit-Id: c740d403708862514be9fa24f56b2764328979eb
Original-Change-Id: I84f33d75ea7ebfea180b304e8ff683884f0dbe8a
Original-Signed-off-by: Kane Chen <kane.chen at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241754
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/baytrail/chip.h | 1 +
src/soc/intel/baytrail/ramstage.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 97b92ef..ecf1ce3 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -88,6 +88,7 @@ struct soc_intel_baytrail_config {
uint16_t gpu_pipeb_light_off_delay;
uint16_t gpu_pipeb_power_cycle_delay;
int gpu_pipeb_pwm_freq_hz;
+ int disable_ddr_2x_refresh_rate;
};
extern struct chip_operations soc_intel_baytrail_ops;
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 6c2de11..8b6d93c 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -38,6 +38,7 @@
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/ramstage.h>
+#include <soc/iosf.h>
/* Global PATTRS */
DEFINE_PATTRS;
@@ -170,12 +171,24 @@ static void s3_resume_prepare(void)
s3_save_acpi_wake_source(gnvs);
}
+static void baytrail_enable_2x_refresh_rate(void)
+{
+ u32 reg;
+ reg = iosf_dunit_read(0x8);
+ reg = reg & ~0x7000;
+ reg = reg | 0x2000;
+ iosf_dunit_write(0x8, reg);
+}
+
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
{
struct soc_gpio_config *gpio_config;
fill_in_pattrs();
+ if (!config->disable_ddr_2x_refresh_rate)
+ baytrail_enable_2x_refresh_rate();
+
/* Allow for SSE instructions to be executed. */
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
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