[coreboot-gerrit] New patch to review for coreboot: eb699a6 google/rush_ryu: devicetree: Add dsi panel mode settings
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Apr 10 13:17:36 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9516
-gerrit
commit eb699a6892da71ccce3c11c1a71241d273acd1b1
Author: Jimmy Zhang <jimmzhang at nvidia.com>
Date: Fri Nov 14 14:50:47 2014 -0800
google/rush_ryu: devicetree: Add dsi panel mode settings
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I2bd1b2c2b1bfe75702a12129ca57b3afa6542575
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 6aac5ecb014ab213f465b9aa78f587994c6b3624
Original-Change-Id: I64f2df49a258b4dd024305a9757704a823265e99
Original-Signed-off-by: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229911
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/rush_ryu/devicetree.cb | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/src/mainboard/google/rush_ryu/devicetree.cb b/src/mainboard/google/rush_ryu/devicetree.cb
index 98284fc..c0af141 100644
--- a/src/mainboard/google/rush_ryu/devicetree.cb
+++ b/src/mainboard/google/rush_ryu/devicetree.cb
@@ -24,4 +24,26 @@ chip soc/nvidia/tegra132
device cpu 0 on end
device cpu 1 on end
end
+
+ register "display_controller" = "TEGRA_ARM_DISPLAYA"
+ register "xres" = "2560"
+ register "yres" = "1800"
+
+ # bits per pixel and color depth
+ register "framebuffer_bits_per_pixel" = "32"
+ register "color_depth" = "12"
+
+ register "href_to_sync" = "1"
+ register "hfront_porch" = "80"
+ register "hsync_width" = "80"
+ register "hback_porch" = "80"
+
+ register "vref_to_sync" = "1"
+ register "vfront_porch" = "4"
+ register "vsync_width" = "4"
+ register "vback_porch" = "4"
+ register "refresh" = "60"
+
+ # kernel driver
+ register "pixel_clock" = "301620000"
end
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