[coreboot-gerrit] New patch to review for coreboot: 55aebc4 tegra132: Change memlayout to have PRERAM and POSTRAM CBFS Cache
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Apr 10 13:18:33 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9535
-gerrit
commit 55aebc49d58ef1074944db59fe013082fcf9e051
Author: Furquan Shaikh <furquan at google.com>
Date: Fri Nov 21 17:04:42 2014 -0800
tegra132: Change memlayout to have PRERAM and POSTRAM CBFS Cache
Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split
them into PRERAM and POSTRAM CBFS_CACHE.
BUG=None
BRANCH=None
TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu.
Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf
Original-Reviewed-on: https://chromium-review.googlesource.com/231546
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
---
src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
index afc4538..b990f54 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
@@ -33,7 +33,7 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- CBFS_CACHE(0x40002000, 72K)
+ PRERAM_CBFS_CACHE(0x40002000, 72K)
VBOOT2_WORK(0x40014000, 16K)
STACK(0x40018000, 2K)
BOOTBLOCK(0x40019000, 20K)
@@ -44,5 +44,6 @@ SECTIONS
SRAM_END(0x40040000)
DRAM_START(0x80000000)
+ POSTRAM_CBFS_CACHE(0x80100000, 1M)
RAMSTAGE(0x80200000, 256K)
}
More information about the coreboot-gerrit
mailing list