[coreboot-gerrit] New patch to review for coreboot: b8ed3d8 rk3288: Increase the delay to 10us when DDR revoked reset.
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri Apr 10 22:34:32 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9578
-gerrit
commit b8ed3d85181f2fc0c8b92b705fadb7c7fc6705ac
Author: Dailunxue <lunxue.dai at rock-chips.com>
Date: Wed Dec 3 16:03:23 2014 +0800
rk3288: Increase the delay to 10us when DDR revoked reset.
After DDR PHY reset de-asserted, DLL automatically starts to
lock, and the lock time is maximum 5.12us. The output clock of
DLL supplies the clocks of DDR controller and PHY digital logic.
So before DLL lock, the clocks of DDR controller and PHY digital
logic are indeterminate. When programming DDR in the period of
DLL unlock, the programming maybe unstable because of the
indeterminate clocks. So we need wait for at least 5.12us after
de-asserting reset, then start to program DDR registers.
Add some redundancy, the waiting time hopes to achieve 10us.
BUG=chrome-os-partner:33148
TEST=I'm using the following command line test ok(15000 cycles).
"while sleep 4 && dut-control cold_reset:on sleep:.1 cold_reset:off;
do : ; done"
BRANCH=None
Change-Id: Ie7d615f5a2264c615c4b4413d6b828cd3d78cd2b
Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Original-Commit-Id: 54e1a439c0e29aaf4fc542ae756f7bb036ceaf3e
Original-Change-Id: I55f8cb11ed3d7962567c5f40a31e6c8aed8fdcb0
Original-Signed-off-by: DaiLunXue <dlx at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/232894
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Commit-Queue: Lunxue Dai <lunxue.dai at rock-chips.com>
Original-Tested-by: Lunxue Dai <lunxue.dai at rock-chips.com>
---
src/soc/rockchip/rk3288/sdram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index d49b860..5a158ad 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -531,7 +531,7 @@ static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs,
rkclk_ddr_reset(channel, 1, 0);
udelay(10);
rkclk_ddr_reset(channel, 0, 0);
- udelay(1);
+ udelay(10);
}
static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs,
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