[coreboot-gerrit] New patch to review for coreboot: d446617 urara: add support for DMA coherent memory area
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri Apr 10 22:44:10 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9593
-gerrit
commit d4466172a803f714d53fdf10977d9326e139f169
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Fri Dec 12 13:53:22 2014 +0000
urara: add support for DMA coherent memory area
The information about the DMA memory area is further passed
through the coreboot table to the payload.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA; DMA memory area was used to test the
functionality of the DWC2 USB controller driver; behavior was
as expected.
BRANCH=none
Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133
Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a
Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/235910
Original-Reviewed-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb at chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb at chromium.org>
---
src/arch/mips/include/arch/memlayout.h | 2 +-
src/mainboard/google/urara/mainboard.c | 14 +++++++++++++-
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h
index 4cbbe1d..0b30338 100644
--- a/src/arch/mips/include/arch/memlayout.h
+++ b/src/arch/mips/include/arch/memlayout.h
@@ -26,6 +26,6 @@
/* TODO: Double-check that that's the correct alignment for our ABI. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
-/* TODO: Need to add DMA_COHERENT region like on ARM? */
+#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c
index 1909fc8..0a0cb02 100644
--- a/src/mainboard/google/urara/mainboard.c
+++ b/src/mainboard/google/urara/mainboard.c
@@ -18,9 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
-
+#include <arch/io.h>
+#include <symbols.h>
#include <console/console.h>
#include <device/device.h>
+#include <boot/coreboot_tables.h>
static void mainboard_enable(device_t dev)
{
@@ -31,3 +33,13 @@ struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
+void lb_board(struct lb_header *header)
+{
+ struct lb_range *dma;
+
+ dma = (struct lb_range *)lb_new_record(header);
+ dma->tag = LB_TAB_DMA;
+ dma->size = sizeof(*dma);
+ dma->range_start = (uintptr_t)_dma_coherent;
+ dma->range_size = _dma_coherent_size;
+}
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 1c7ea9a..c3c6c07 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -36,4 +36,6 @@ SECTIONS
/* Let's use SRAM for CBFS cache. */
CBFS_CACHE(0x9b000000, 64K)
+ /* DMA coherent area: end of available DRAM, uncached */
+ DMA_COHERENT(0xAFF00000, 1M)
}
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