[coreboot-gerrit] Patch merged into coreboot/master: f9ff353 spi: support controllers with limited transfer size capabilities
gerrit at coreboot.org
gerrit at coreboot.org
Mon Apr 13 13:01:54 CEST 2015
the following patch was just integrated into master:
commit f9ff353430aae70e5cc04fb32d983b572956bd7d
Author: Vadim Bendebury <vbendeb at chromium.org>
Date: Sat Nov 29 15:06:26 2014 -0800
spi: support controllers with limited transfer size capabilities
Some SPI controllers (like Imgtec Pistachio), have a hard limit on SPI
read and write transactions. Limiting transfer size in the wrapper
allows to provide the API user with unlimited transfer size
transactions.
The tranfer size limitation is added to the spi_slave structure, which
is set up by the controller driver. The value of zero in this field
means 'unlimited transfer size'. It will work with existion drivers,
as they all either keep structures in the bss segment, or initialize
them to all zeros.
This patch addresses the problem for reads only, as coreboot is not
expected to require to write long chunks into SPI devices.
BRANCH=none
BUG=chrome-os-partner:32441, chrome-os-partner:31438
TEST=set transfer size limit to artificially low value (4K) and
observed proper operation on both Pistachio and ipq8086: both
Storm and Urara booted through romstage and ramstage.
Change-Id: Ibb96aa499c3eec458c94bf1193fbbbf5f54e1477
Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Original-Commit-Id: 4f064fdca5b6c214e7a7f2751dc24e33cac2ea45
Original-Change-Id: I9df24f302edc872bed991ea450c0af33a1c0ff7b
Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232239
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
Reviewed-on: http://review.coreboot.org/9571
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi at google.com>
See http://review.coreboot.org/9571 for details.
-gerrit
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