[coreboot-gerrit] Patch set updated for coreboot: 975336b rk3288: Add CBMEM console support and fix RETURN_FROM_VERSTAGE
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Apr 13 18:22:05 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9607
-gerrit
commit 975336b76d4a58ece885bfa68de4abf1a635fa9e
Author: Julius Werner <jwerner at chromium.org>
Date: Mon Dec 1 13:28:47 2014 -0800
rk3288: Add CBMEM console support and fix RETURN_FROM_VERSTAGE
Since we can now reduce our vboot2 work buffer by 4K, we can use all
that hard-earned space for the CBMEM console instead (and 4K are
unfortunately barely enough for all the stuff we dump with vboot2).
Also add console_init() and exception_init() to the verstage for
CONFIG_RETURN_FROM_VERSTAGE, which was overlooked before (our model
requires those functions to be called again at the beginning of every
stage... even though some consoles like UARTs might not need it, others
like the CBMEM console do). In the !RETURN_FROM_VERSTAGE case, this is
expected to be done by the platform-specific verstage entry wrapper, and
already in place for the only implementation we have for now (tegra124).
(Technically, there is still a bug in the case where EARLY_CONSOLE is
set but BOOTBLOCK_CONSOLE isn't, since both verstage and romstage would
run init_console_ptr() as if they were there first, so the romstage
overwrites the verstage's output. I don't think it's worth fixing that
now, since EARLY_CONSOLE && !BOOTBLOCK_CONSOLE is a pretty pointless
use-case and I think we should probably just get rid of the
CONFIG_BOOTBLOCK_CONSOLE option eventually.)
BRANCH=None
BUG=None
TEST=Booted Pinky.
Change-Id: I87914df3c72f0262eb89f337454009377a985497
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 85486928abf364c5d5d1cf69f7668005ddac023c
Original-Change-Id: Id666cb7a194d32cfe688861ab17c5e908bc7760d
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232614
---
src/arch/arm/include/armv4/arch/exception.h | 2 +-
src/arch/x86/include/arch/exception.h | 2 +-
src/soc/rockchip/rk3288/include/soc/memlayout.ld | 9 +++++----
src/vendorcode/google/chromeos/vboot2/verstage.c | 14 ++++++++++----
4 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/include/armv4/arch/exception.h b/src/arch/arm/include/armv4/arch/exception.h
index a426c52..d4e9658 100644
--- a/src/arch/arm/include/armv4/arch/exception.h
+++ b/src/arch/arm/include/armv4/arch/exception.h
@@ -30,6 +30,6 @@
#ifndef _ARCH_EXCEPTION_H
#define _ARCH_EXCEPTION_H
-static void exception_init(void) { /* not implemented */ }
+static inline void exception_init(void) { /* not implemented */ }
#endif
diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h
index a426c52..d4e9658 100644
--- a/src/arch/x86/include/arch/exception.h
+++ b/src/arch/x86/include/arch/exception.h
@@ -30,6 +30,6 @@
#ifndef _ARCH_EXCEPTION_H
#define _ARCH_EXCEPTION_H
-static void exception_init(void) { /* not implemented */ }
+static inline void exception_init(void) { /* not implemented */ }
#endif
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index 922e2f8..e5c44a0 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -35,15 +35,16 @@ SECTIONS
SRAM_START(0xFF700000)
TTB(0xFF700000, 16K)
BOOTBLOCK(0xFF704004, 15K - 4)
- TTB_SUBTABLES(0xFF707c00, 1K)
- VBOOT2_WORK(0xFF708000, 16K)
+ TTB_SUBTABLES(0xFF707C00, 1K)
+ PRERAM_CBMEM_CONSOLE(0xFF708000, 4K)
+ VBOOT2_WORK(0xFF709000, 12K)
OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K)
PRERAM_CBFS_CACHE(0xFF716000, 4K)
STACK(0xFF717000, 4K)
SRAM_END(0xFF718000)
- /* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit
- * wide write accesses! Only use with MMU and writeback mapping. */
+ /* 4K of special SRAM in PMU power domain.
+ * Careful: only supports 32-bit wide write accesses! */
SYMBOL(pmu_sram, 0xFF720000)
SYMBOL(epmu_sram, 0xFF721000)
}
diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.c b/src/vendorcode/google/chromeos/vboot2/verstage.c
index 88c18f6..289b93f 100644
--- a/src/vendorcode/google/chromeos/vboot2/verstage.c
+++ b/src/vendorcode/google/chromeos/vboot2/verstage.c
@@ -18,6 +18,7 @@
*/
#include <antirollback.h>
+#include <arch/exception.h>
#include <console/console.h>
#include <console/vtxprintf.h>
#include <string.h>
@@ -166,11 +167,7 @@ static void save_if_needed(struct vb2_context *ctx)
* TODO: Avoid loading a stage twice (once in hash_body & again in load_stage).
* when per-stage verification is ready.
*/
-#if CONFIG_RETURN_FROM_VERSTAGE
-void main(void)
-#else
void verstage_main(void)
-#endif /* CONFIG_RETURN_FROM_VERSTAGE */
{
struct vb2_context ctx;
struct vboot_region fw_main;
@@ -249,3 +246,12 @@ void verstage_main(void)
printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B');
vb2_set_selected_region(wd, &fw_main);
}
+
+#if IS_ENABLED(CONFIG_RETURN_FROM_VERSTAGE)
+void main(void)
+{
+ console_init();
+ exception_init();
+ verstage_main();
+}
+#endif
More information about the coreboot-gerrit
mailing list