[coreboot-gerrit] New patch to review for coreboot: 843ea1f broadwell: Fixes for _SWS support
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Wed Apr 15 01:45:07 CEST 2015
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9699
-gerrit
commit 843ea1f483622c5203e7ab4c0dae648436088d2a
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Fri Dec 12 10:52:34 2014 -0800
broadwell: Fixes for _SWS support
- These should be 64bit values so when they try to return -1
it is interpreted properly by the kernel.
- The GPE value needs to be reset at the start so it does not
return stale data from a previous resume.
- If a GPE register is zero the value should only be updated
if it has not yet found a set bit.
BUG=chrome-os-partner:34532
BRANCH=samus,auron
TEST=build and boot on samus, suspend/resume with various
wake sources and ensure the reported _SWS values are correct
in every case.
Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/235012
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
(cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a
---
src/soc/intel/broadwell/acpi/globalnvs.asl | 19 +++++++++----------
src/soc/intel/broadwell/include/soc/nvs.h | 22 ++++++++++------------
src/soc/intel/broadwell/ramstage.c | 6 ++++--
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index 9bddbc2..223d21a 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -53,16 +53,15 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TCRT, 8, // 0x10 - Critical Threshold
TPSV, 8, // 0x11 - Passive Threshold
TMAX, 8, // 0x12 - CPU Tj_max
- , 8, // 0x13 - Unused
- S5U0, 8, // 0x14 - Enable USB in S5
- S3U0, 8, // 0x15 - Enable USB in S3
- S33G, 8, // 0x16 - Enable 3G in S3
- LIDS, 8, // 0x17 - LID State
- PWRS, 8, // 0x18 - AC Power State
- CMEM, 32, // 0x19 - 0x1c - CBMEM TOC
- CBMC, 32, // 0x1d - 0x20 - Coreboot Memory Console
- PM1I, 32, // 0x21 - 0x24 - PM1 wake status bit
- GPEI, 32, // 0x25 - 0x28 - GPE wake status bit
+ S5U0, 8, // 0x13 - Enable USB in S5
+ S3U0, 8, // 0x14 - Enable USB in S3
+ S33G, 8, // 0x15 - Enable 3G in S3
+ LIDS, 8, // 0x16 - LID State
+ PWRS, 8, // 0x17 - AC Power State
+ CMEM, 32, // 0x18 - 0x1b - CBMEM TOC
+ CBMC, 32, // 0x1c - 0x1f - Coreboot Memory Console
+ PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
+ GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 2f835c8..6dcd9ba 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -44,17 +44,16 @@ typedef struct {
u8 tcrt; /* 0x10 - Critical Threshold */
u8 tpsv; /* 0x11 - Passive Threshold */
u8 tmax; /* 0x12 - CPU Tj_max */
- u8 unused1; /* 0x13 - Unused */
- u8 s5u0; /* 0x14 - Enable USB in S5 */
- u8 s3u0; /* 0x15 - Enable USB in S3 */
- u8 s33g; /* 0x16 - Enable 3G in S3 */
- u8 lids; /* 0x17 - LID State */
- u8 pwrs; /* 0x18 - AC Power State */
- u32 obsolete_cmem; /* 0x19 - 0x1c - CBMEM TOC */
- u32 cbmc; /* 0x1d - 0x20 - Coreboot Memory Console */
- u32 pm1i; /* 0x21 - 0x24 - PM1 wake status bit */
- u32 gpei; /* 0x25 - 0x28 - GPE wake status bit */
- u8 unused[215];
+ u8 s5u0; /* 0x13 - Enable USB in S5 */
+ u8 s3u0; /* 0x14 - Enable USB in S3 */
+ u8 s33g; /* 0x15 - Enable 3G in S3 */
+ u8 lids; /* 0x16 - LID State */
+ u8 pwrs; /* 0x17 - AC Power State */
+ u32 cmem; /* 0x18 - 0x1b - CBMEM TOC */
+ u32 cbmc; /* 0x1c - 0x1f - Coreboot Memory Console */
+ u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */
+ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */
+ u8 unused[208];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
@@ -63,7 +62,6 @@ typedef struct {
device_nvs_t dev;
} __attribute__((packed)) global_nvs_t;
-void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index c9a422f..eaa28d0 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -52,13 +52,15 @@ static void save_acpi_wake_source(global_nvs_t *gnvs)
gnvs->pm1i = -1;
/* Scan for first set bit in GPE registers */
+ gnvs->gpei = -1;
for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) {
u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg];
int start = gpe_reg * GPE0_REG_SIZE;
int end = start + GPE0_REG_SIZE;
if (gpe == 0) {
- gnvs->gpei = end;
+ if (!gnvs->gpei)
+ gnvs->gpei = end;
continue;
}
@@ -73,7 +75,7 @@ static void save_acpi_wake_source(global_nvs_t *gnvs)
if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE))
gnvs->gpei = -1;
- printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %d GPE Index %d\n",
+ printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n",
gnvs->pm1i, gnvs->gpei);
}
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