[coreboot-gerrit] Patch set updated for coreboot: e24e92e veyron: support H5TC4G63CFR sdram in jerry
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Apr 15 21:56:53 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9635
-gerrit
commit e24e92eeba75c87b4f7d1e2756118ea13dfb0fee
Author: huang lin <hl at rock-chips.com>
Date: Thu Dec 18 12:32:56 2014 +0800
veyron: support H5TC4G63CFR sdram in jerry
BRANCH=None
TEST=Boot and run jerry rev2 board
BUG=None
Change-Id: I95ec99e444c9cff3008bac5d1e6c3365fc2229a0
Signed-off-by: Stefan Reinauer <reinauer at chromium.org>
Original-Commit-Id: f9075e6172d1ae503dc26bac8f1057455dc93c39
Original-Change-Id: Ice60a4576c9eb386599a545c1b8d470e8a2eed68
Original-Signed-off-by: huang lin <hl at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/236500
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-Commit-Queue: Paul Ma <magf at bitland.com.cn>
Original-Tested-by: Paul Ma <magf at bitland.com.cn>
---
src/mainboard/google/veyron_jerry/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-hynix-2GB.inc | 55 +++++++++++-----------
2 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c
index 3593758..b997b0a 100644
--- a/src/mainboard/google/veyron_jerry/sdram_configs.c
+++ b/src/mainboard/google/veyron_jerry/sdram_configs.c
@@ -30,7 +30,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
+#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
index 07161c0..fd42471 100644
--- a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
+++ b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-2GB.inc
@@ -1,4 +1,5 @@
{
+ /* 4 Hynic H5TC4G63CFR chips */
{
{
.rank = 0x1,
@@ -22,54 +23,54 @@
}
},
{
- .togcnt1u = 0x215,
+ .togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
- .togcnt100n = 0x35,
+ .togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
- .trfc = 0xBB,
- .trp = 0x8,
- .trtw = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
.tal = 0x0,
- .tcl = 0x8,
- .tcwl = 0x6,
- .tras = 0x14,
- .trc = 0x1D,
- .trcd = 0x8,
- .trrd = 0x6,
- .trtp = 0x4,
- .twr = 0x8,
- .twtr = 0x4,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
.texsr = 0x200,
- .txp = 0x4,
- .txpdll = 0xD,
+ .txp = 0x5,
+ .txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
- .tcksre = 0x6,
- .tcksrx = 0x6,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
- .trstl = 0x36,
+ .trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
- .dtpr0 = 0x3AD48890,
- .dtpr1 = 0xBB08D8,
- .dtpr2 = 0x1002B600,
- .mr[0] = 0x840,
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
.mr[1] = 0x40,
- .mr[2] = 0x8,
+ .mr[2] = 0x10,
.mr[3] = 0x0
},
- .noc_timing = 0x2891E41D,
- .noc_activate = 0x5B6,
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
.ddrconfig = 3,
- .ddr_freq = 533*MHz,
+ .ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
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