[coreboot-gerrit] Patch set updated for coreboot: 3fe3d70 southbridge/bd82x6x: use new ssdt sata port generator
Alexander Couzens (lynxis@fe80.eu)
gerrit at coreboot.org
Thu Apr 16 15:32:46 CEST 2015
Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709
-gerrit
commit 3fe3d70c2f5971b235ed0dd8bcb6f481625fd269
Author: Alexander Couzens <lynxis at fe80.eu>
Date: Thu Apr 16 02:00:21 2015 +0200
southbridge/bd82x6x: use new ssdt sata port generator
Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0
Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
src/southbridge/intel/bd82x6x/Makefile.inc | 1 +
src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 -----------------------------
src/southbridge/intel/bd82x6x/sata.c | 7 ++++
3 files changed, 8 insertions(+), 52 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 83de051..0e74b1c 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -28,6 +28,7 @@ ramstage-y += lpc.c
ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sata.c
+ramstage-y += ../common/sata.c
ramstage-y += usb_ehci.c
ramstage-y += usb_xhci.c
ramstage-y += me.c
diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl
index ba737a7..f515b3f 100644
--- a/src/southbridge/intel/bd82x6x/acpi/sata.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl
@@ -27,56 +27,4 @@
Device (SATA)
{
Name (_ADR, 0x001f0002)
-
- Device (PRID)
- {
- Name (_ADR, 0)
-
- // Get Timing Mode
- Method (_GTM)
- {
- Name(PBUF, Buffer(20) {
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00 })
-
- CreateDwordField (PBUF, 0, PIO0)
- CreateDwordField (PBUF, 4, DMA0)
- CreateDwordField (PBUF, 8, PIO1)
- CreateDwordField (PBUF, 12, DMA1)
- CreateDwordField (PBUF, 16, FLAG)
-
- // TODO fill return structure
-
- Return (PBUF)
- }
-
- // Set Timing Mode
- Method (_STM, 3)
- {
- CreateDwordField (Arg0, 0, PIO0)
- CreateDwordField (Arg0, 4, DMA0)
- CreateDwordField (Arg0, 8, PIO1)
- CreateDwordField (Arg0, 12, DMA1)
- CreateDwordField (Arg0, 16, FLAG)
-
- // TODO: Do the deed
- }
-
- Device (DSK0)
- {
- Name (_ADR, 0)
- // TODO: _RMV ?
- // TODO: _GTF ?
- }
-
- Device (DSK1)
- {
- Name (_ADR, 1)
-
- // TODO: _RMV ?
- // TODO: _GTF ?
- }
-
- }
}
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index cf3b14e..e4450ee 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -25,6 +25,7 @@
#include <device/pci_ids.h>
#include "pch.h"
#include <pc80/mc146818rtc.h>
+#include <southbridge/intel/common/sata.h>
typedef struct southbridge_intel_bd82x6x_config config_t;
@@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+static void sata_fill_ssdt(device_t dev) {
+ config_t *config = dev->chip_info;
+ intel_generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map);
+}
+
static struct pci_operations sata_pci_ops = {
.set_subsystem = sata_set_subsystem,
};
@@ -255,6 +261,7 @@ static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_fill_ssdt_generator = sata_fill_ssdt,
.init = sata_init,
.enable = sata_enable,
.scan_bus = 0,
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