[coreboot-gerrit] Patch merged into coreboot/master: deaaab2 arch/mips: Fix bug when performing cache operations
gerrit at coreboot.org
gerrit at coreboot.org
Fri Apr 17 09:23:34 CEST 2015
the following patch was just integrated into master:
commit deaaab25365b093229836d4294b1868093df7c47
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Wed Jan 21 01:51:25 2015 +0000
arch/mips: Fix bug when performing cache operations
Each type of cache might have different cache line size.
Call the proper get_<*>cache_line function for each cache
type.
Fixes problem with get_L2cache_line which previously
targeted L3 cache line in the config register, instead of
L2 cache.
TODO: add support for tertiary caches and have cache
operations be called per CPU, not per architecture.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; worked as expected;
BRANCH=none
Change-Id: I7de946cbd6bac716e99fe07cb0deb5aa76c84171
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 62e2803c6f2a3ad02dc88f50a4ae2ea00487e3f4
Original-Change-Id: I03071f24aacac1805cfd89e4f44b14ed1c1e984e
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241853
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
Reviewed-on: http://review.coreboot.org/9731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
See http://review.coreboot.org/9731 for details.
-gerrit
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