[coreboot-gerrit] Patch set updated for coreboot: a478668 Intel(R) 945G: Fix "enable upper 128bytes of CMOS"
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Mon Apr 20 09:37:41 CEST 2015
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9801
-gerrit
commit a4786684bf97e4000e8125b1c561609e66a7eb47
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Apr 19 10:58:41 2015 +0200
Intel(R) 945G: Fix "enable upper 128bytes of CMOS"
Default RCBA32(RC) value is 0.
We should use "RCBA32(RC) |= (1 << 2);" to enable upper 128bytes.
No need to "enable" it again in "raminit.c" file.
Change-Id: I12d8689b5b5238f46fa834b9d30bf689eb0c8114
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/intel/i945/early_init.c | 2 +-
src/northbridge/intel/i945/raminit.c | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 776c051..ea92ce1 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -172,7 +172,7 @@ static void i945_setup_bars(void)
printk(BIOS_DEBUG, " done.\n");
/* Enable upper 128bytes of CMOS */
- RCBA32(0x3400) = (1 << 2);
+ RCBA32(RC) |= (1 << 2);
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c3f9bae..bd6e0c9 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2738,8 +2738,6 @@ static void sdram_program_receive_enable(struct sys_info *sysinfo)
{
MCHBAR32(REPC) |= (1 << 0);
- /* enable upper CMOS */
- RCBA32(0x3400) = (1 << 2);
/* Program Receive Enable Timings */
if (sysinfo->boot_path == BOOT_PATH_RESUME) {
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