[coreboot-gerrit] New patch to review for coreboot: 83e33df broadwell: indent xhci code
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Apr 20 10:30:28 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9813
-gerrit
commit 83e33df5c5256330f958039438e5a0da48d69a98
Author: Patrick Georgi <pgeorgi at chromium.org>
Date: Mon Apr 20 10:27:59 2015 +0200
broadwell: indent xhci code
Change-Id: I97920e7eb64c05034184f9a4e1c8f2dfa44d3fdd
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
---
src/soc/intel/broadwell/xhci.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index fde8bf7..cfd0c56 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -162,23 +162,23 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
if (!is_broadwell) {
/* This WA is only for lpt */
- /* Clear PCI 0xB0[14:13] */
- reg32 = pci_read_config32(dev, 0xb0);
- reg32 &= ~((1 << 14) | (1 << 13));
- pci_write_config32(dev, 0xb0, reg32);
-
- /* Clear MMIO 0x816c[14,2] */
- reg32 = read32(mem_base + 0x816c);
- reg32 &= ~((1 << 14) | (1 << 2));
- write32(mem_base + 0x816c, reg32);
-
- /* Reset disconnected USB3 ports */
- usb_xhci_reset_usb3(dev, 0);
-
- /* Set MMIO 0x80e0[15] */
- reg32 = read32(mem_base + 0x80e0);
- reg32 |= (1 << 15);
- write32(mem_base + 0x80e0, reg32);
+ /* Clear PCI 0xB0[14:13] */
+ reg32 = pci_read_config32(dev, 0xb0);
+ reg32 &= ~((1 << 14) | (1 << 13));
+ pci_write_config32(dev, 0xb0, reg32);
+
+ /* Clear MMIO 0x816c[14,2] */
+ reg32 = read32(mem_base + 0x816c);
+ reg32 &= ~((1 << 14) | (1 << 2));
+ write32(mem_base + 0x816c, reg32);
+
+ /* Reset disconnected USB3 ports */
+ usb_xhci_reset_usb3(dev, 0);
+
+ /* Set MMIO 0x80e0[15] */
+ reg32 = read32(mem_base + 0x80e0);
+ reg32 |= (1 << 15);
+ write32(mem_base + 0x80e0, reg32);
}
reg32 = read32(mem_base + 0x8154);
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