[coreboot-gerrit] Patch set updated for coreboot: cc5c327 pistachio: Decrease DDR ODT from 75R to 50R
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Apr 20 17:07:45 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9846
-gerrit
commit cc5c327c23e68815a7ae5104a0b2aa0a75e2e4a0
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Thu Mar 5 17:11:14 2015 +0000
pistachio: Decrease DDR ODT from 75R to 50R
The DDR On Die Termination was incorrectly configured at 75R,
where as the data sheet suggests for DDR2-800 it should be
set to 50R.
Correct this by adjusting the ODT setting in the EMR register.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
BRANCH=none
Change-Id: I2f0242c422b1cb3d1f64ce3dd17b62fef5e7e155
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: ac081ac59c0dc3d16a7b540cd379fb870b6cfe40
Original-Change-Id: If7951812033c4e88f4be3c143fb49526eddba142
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256304
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
---
src/soc/imgtec/pistachio/ddr2_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index e236c1c..0943cfa 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -240,7 +240,7 @@ int init_ddr2(void)
* 15:13 RSVD
* 31:16 Reserved
*/
- write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000004);
+ write32(DDR_PHY + DDRPHY_EMR_OFFSET, 0x00000044);
/* MR2 : EMR2 Register
* Generate to use with PHY and PCTL
* 2:0 PASR, NA 000
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