[coreboot-gerrit] Patch set updated for coreboot: e9a4b7e qualcomm/ipq806x: report versions of RPM and DDR init components
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Apr 21 10:44:06 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9860
-gerrit
commit e9a4b7e2fabada874df6dc2a8eb1355c22e2eaa3
Author: Vadim Bendebury <vbendeb at chromium.org>
Date: Thu Mar 5 17:36:00 2015 -0800
qualcomm/ipq806x: report versions of RPM and DDR init components
DDR init blob version string can be found at a fixed location in
memory once the blob is loaded. Maximum size of the string is 48
bytes.
The RPM RW version is defined in a 32 bit version stored at yet
another fixed address once RPM RW has started.
BRANCH=storm
BUG=chrome-os-partner:30623
TEST=ran this command on the booted system:
localhost ~ # egrep '(DDR|RPM)' /sys/firmware/log
Loaded DDR init blob version 99ce41d at -AAABANAZA
DDR initialized
Starting RPM
Started RPM version 1.0.128
localhost ~ #
Change-Id: If3c3c8368845b978605ccfda7e09c21ae2e5ab9a
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 328c9c57cf93110bc0fdd267134d72e386d70834
Original-Change-Id: If411f6f7bca53ea20390b7e851cb3d120681eade
Original-Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/256738
Original-Reviewed-by: Varadarajan Narayanan <varada at qti.qualcomm.com>
---
src/soc/qualcomm/ipq806x/blobs_init.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c
index d513d25..e3478a9 100644
--- a/src/soc/qualcomm/ipq806x/blobs_init.c
+++ b/src/soc/qualcomm/ipq806x/blobs_init.c
@@ -65,6 +65,9 @@ static void *load_ipq_blob(const char *file_name)
#ifdef __PRE_RAM__
+#define DDR_VERSION() ((const char *)0x2a03f600)
+#define MAX_DDR_VERSION_SIZE 48
+
int initialize_dram(void)
{
void *cdt;
@@ -82,7 +85,12 @@ int initialize_dram(void)
if (ddr_init_function(cdt) < 0)
die("Fail to Initialize DDR\n");
- printk(BIOS_INFO, "DDR initialized\n");
+ /*
+ * Once DDR initializer finished, its verison can be found at a fixed
+ * address in SRAM.
+ */
+ printk(BIOS_INFO, "DDR version %.*s initialized\n",
+ MAX_DDR_VERSION_SIZE, DDR_VERSION());
return 0;
}
@@ -101,10 +109,14 @@ void start_tzbsp(void)
tz_init_wrapper(0, 0, tzbsp);
}
+/* RPM version is encoded in a 32 bit word at the fixed address */
+#define RPM_VERSION() (*((u32 *)(0x00108008)))
void start_rpm(void)
{
u32 load_addr;
u32 ready_mask = 1 << 10;
+ u32 rpm_version;
+
struct stopwatch sw;
if (read32(RPM_SIGNAL_COOKIE) == RPM_FW_MAGIC_NUM) {
@@ -134,5 +146,12 @@ void start_rpm(void)
/* Acknowledge RPM initialization */
write32(RPM_INT_ACK, ready_mask);
+
+ /* Report RPM version, it is encoded in a 32 bit value. */
+ rpm_version = RPM_VERSION();
+ printk(BIOS_INFO, "Started RPM version %d.%d.%d\n",
+ rpm_version >> 24,
+ (rpm_version >> 16) & 0xff,
+ rpm_version & 0xffff);
}
#endif /* !__PRE_RAM__ */
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