[coreboot-gerrit] Patch set updated for coreboot: 1a83185 i945/raminit.c: fix write Cache Control for 82945G/GZ/P/PL
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Thu Apr 23 14:36:42 CEST 2015
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9971
-gerrit
commit 1a8318501250a01849a631a696ee6b8a98e4bef6
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Thu Apr 23 12:10:17 2015 +0200
i945/raminit.c: fix write Cache Control for 82945G/GZ/P/PL
Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/intel/i945/raminit.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index bd6e0c9..f18780c 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2326,8 +2326,14 @@ static void sdram_pre_jedec_initialization(void)
u32 reg32;
reg32 = MCHBAR32(WCC);
- reg32 &= 0x113ff3ff;
- reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
+ if (pci_read_config32(PCI_DEV(0, 0x00,0), 0x02) == 0x2770)
+ {
+ reg32 &= 0xf3fff7ff;
+ reg32 |= (1 << 25) | (3 << 22) | (1 << 10);
+ } else {
+ reg32 &= 0x113ff3ff;
+ reg32 |= (4 << 29) | (3 << 25) | (1 << 10);
+ }
MCHBAR32(WCC) = reg32;
MCHBAR32(SMVREFC) |= (1 << 6);
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