[coreboot-gerrit] New patch to review for coreboot: glados: Enable wake from EC via LAN_WAKE#

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11171

-gerrit

commit 5ed9cafcc55c15afd18079e762215935c7bf3dd3
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Jul 24 15:39:31 2015 -0700

    glados: Enable wake from EC via LAN_WAKE#
    
    Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#.
    Report the EC wake pin LAN_WAKE as GPE[112].
    
    BUG=chrome-os-partner:43079
    BRANCH=none
    TEST=suspend/resume on glados with wake from keyboard
    
    Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/288921
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/glados/acpi/mainboard.asl | 3 +++
 src/mainboard/google/glados/devicetree.cb      | 1 +
 2 files changed, 4 insertions(+)

diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl
index 7c26e42..53001e4 100644
--- a/src/mainboard/google/glados/acpi/mainboard.asl
+++ b/src/mainboard/google/glados/acpi/mainboard.asl
@@ -29,6 +29,9 @@ Scope (\_SB)
 		{
 			Return (\_SB.PCI0.LPCB.EC0.LIDS)
 		}
+
+		/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+		Name (_PRW, Package(){ 112, 5 }) /* LAN_WAKE_EN */
 	}
 
 	Device (PWRB)
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 6f89063..b48556f 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -3,6 +3,7 @@ chip soc/intel/skylake
 	# Enable deep Sx states
 	register "deep_s3_enable" = "1"
 	register "deep_s5_enable" = "1"
+	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{ \