[coreboot-gerrit] New patch to review for coreboot: skylake: pass IED_REGION_SIZE Kconfig to FSP

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11199

-gerrit

commit c9a4d3e000946a87be4021135440d77a97888c49
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Aug 5 17:33:49 2015 -0500

    skylake: pass IED_REGION_SIZE Kconfig to FSP
    
    Ignore the devicetree.cb setting and use the already
    existing IED_REGION_SIZE Kconfig option.
    
    BUG=chrome-os-partner:43636
    BRANCH=None
    TEST=Built, booted, suspended, resumed on glados.
    
    Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290931
    Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Trybot-Ready: David James <davidjames at chromium.org>
    
    Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/romstage/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index af9c78b..253eaba 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -99,7 +99,7 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params)
 
 	params->MmioSize = 0x800; /* 2GB in MB */
 	params->TsegSize = CONFIG_SMM_TSEG_SIZE;
-	params->IedSize = config->IedSize;
+	params->IedSize = CONFIG_IED_REGION_SIZE;
 	params->ProbelessTrace = config->ProbelessTrace;
 	params->EnableLan = config->EnableLan;
 	params->EnableSata = config->EnableSata;