[coreboot-gerrit] Patch merged into coreboot/master: intel/common: use external stage cache for fsp_ramstage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit abf87a25f21b22797d8dc8c9a33537980df2c24d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Aug 5 12:26:56 2015 -0500

    intel/common: use external stage cache for fsp_ramstage
    
    The fsp_ramstage.c code was not taking advantage of the stage
    cache which does all the accounting and calculation work for
    the caller. Remove the open coded logic and use the provided
    infrastructure. Using said infrastructure means there's no
    need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove
    it.
    
    BUG=chrome-os-partner:43636
    BRANCH=None
    TEST=Built, booted, suspended, and resumed on glados.
    
    Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290831
    Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy at intel.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
    
    Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/11196
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi <pgeorgi at google.com>


See http://review.coreboot.org/11196 for details.

-gerrit