[coreboot-gerrit] Patch set updated for coreboot: veyron: add Nanya NT5CC256M16DP sdram
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Aug 27 17:29:12 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11399
-gerrit
commit 88f1e4e512c07640d98ff15bcc3212efcf71f547
Author: jinkun.hong <jinkun.hong at rock-chips.com>
Date: Thu Aug 20 14:06:31 2015 +0800
veyron: add Nanya NT5CC256M16DP sdram
BRANCH=None
TEST=Boot from veyron
BUG=None
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101
Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e
Original-Signed-off-by: jinkun.hong <jinkun.hong at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294660
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d)
Original-jwerner: Added Minnie
Original-Signed-off-by: Julius Werner <jwerner at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294763
Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6
---
src/mainboard/google/veyron_brain/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_danger/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_jerry/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_mickey/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_mighty/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_minnie/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_pinky/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_romy/sdram_configs.c | 2 +-
.../veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_shark/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
src/mainboard/google/veyron_speedy/sdram_configs.c | 2 +-
.../sdram_inf/sdram-ddr3-nanya-2GB.inc | 78 ++++++++++++++++++++++
20 files changed, 790 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_brain/sdram_configs.c
+++ b/src/mainboard/google/veyron_brain/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c
index d7db069..84ceba5 100644
--- a/src/mainboard/google/veyron_danger/sdram_configs.c
+++ b/src/mainboard/google/veyron_danger/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_jerry/sdram_configs.c b/src/mainboard/google/veyron_jerry/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_jerry/sdram_configs.c
+++ b/src/mainboard/google/veyron_jerry/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_mickey/sdram_configs.c
+++ b/src/mainboard/google/veyron_mickey/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_mighty/sdram_configs.c b/src/mainboard/google/veyron_mighty/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_mighty/sdram_configs.c
+++ b/src/mainboard/google/veyron_mighty/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_minnie/sdram_configs.c b/src/mainboard/google/veyron_minnie/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_minnie/sdram_configs.c
+++ b/src/mainboard/google/veyron_minnie/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_minnie/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_pinky/sdram_configs.c b/src/mainboard/google/veyron_pinky/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_pinky/sdram_configs.c
+++ b/src/mainboard/google/veyron_pinky/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_romy/sdram_configs.c
+++ b/src/mainboard/google/veyron_romy/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_shark/sdram_configs.c b/src/mainboard/google/veyron_shark/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_shark/sdram_configs.c
+++ b/src/mainboard/google/veyron_shark/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_shark/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
diff --git a/src/mainboard/google/veyron_speedy/sdram_configs.c b/src/mainboard/google/veyron_speedy/sdram_configs.c
index 63e7317..023eb37 100644
--- a/src/mainboard/google/veyron_speedy/sdram_configs.c
+++ b/src/mainboard/google/veyron_speedy/sdram_configs.c
@@ -35,7 +35,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
-#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
diff --git a/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
new file mode 100644
index 0000000..bd82e7b
--- /dev/null
+++ b/src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-nanya-2GB.inc
@@ -0,0 +1,78 @@
+{
+ /* 4 Nanya NT5CC256M16DP chips */
+ {
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ },
+ {
+ .rank = 0x1,
+ .col = 0xA,
+ .bk = 0x3,
+ .bw = 0x2,
+ .dbw = 0x1,
+ .row_3_4 = 0x0,
+ .cs0_row = 0xF,
+ .cs1_row = 0xF
+ }
+ },
+ {
+ .togcnt1u = 0x29A,
+ .tinit = 0xC8,
+ .trsth = 0x1F4,
+ .togcnt100n = 0x42,
+ .trefi = 0x4E,
+ .tmrd = 0x4,
+ .trfc = 0xEA,
+ .trp = 0xA,
+ .trtw = 0x5,
+ .tal = 0x0,
+ .tcl = 0xA,
+ .tcwl = 0x7,
+ .tras = 0x19,
+ .trc = 0x24,
+ .trcd = 0xA,
+ .trrd = 0x7,
+ .trtp = 0x5,
+ .twr = 0xA,
+ .twtr = 0x5,
+ .texsr = 0x200,
+ .txp = 0x5,
+ .txpdll = 0x10,
+ .tzqcs = 0x40,
+ .tzqcsi = 0x0,
+ .tdqs = 0x1,
+ .tcksre = 0x7,
+ .tcksrx = 0x7,
+ .tcke = 0x4,
+ .tmod = 0xC,
+ .trstl = 0x43,
+ .tzqcl = 0x100,
+ .tmrr = 0x0,
+ .tckesr = 0x5,
+ .tdpd = 0x0
+ },
+ {
+ .dtpr0 = 0x48F9AAB4,
+ .dtpr1 = 0xEA0910,
+ .dtpr2 = 0x1002C200,
+ .mr[0] = 0xA60,
+ .mr[1] = 0x40,
+ .mr[2] = 0x10,
+ .mr[3] = 0x0
+ },
+ .noc_timing = 0x30B25564,
+ .noc_activate = 0x627,
+ .ddrconfig = 3,
+ .ddr_freq = 666*MHz,
+ .dramtype = DDR3,
+ .num_channels = 2,
+ .stride = 9,
+ .odt = 1
+},
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