[coreboot-gerrit] New patch to review for coreboot: kunimitsu: Enable and support for DPTF
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Fri Aug 28 10:22:18 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11429
-gerrit
commit 05b028ceaab92e779fdf7c807dacbd9cee19f6f2
Author: Shilpa Sreeramalu <shilpa.sreeramalu at intel.com>
Date: Mon Jun 22 21:54:51 2015 +0530
kunimitsu: Enable and support for DPTF
This patch includes the DPTF specific ASL files in the main
DSDT definition and enables the CPU thermal participant device
in the device tree. It also enables the DPTF flag in the global
NVS table.It also adds the ASL settings specfic to the mainboard.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c
Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu at intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284821
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294650
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch at intel.com>
---
src/mainboard/intel/kunimitsu/acpi/dptf.asl | 100 ++++++++++++++++++++++++++++
src/mainboard/intel/kunimitsu/acpi_tables.c | 1 +
src/mainboard/intel/kunimitsu/dsdt.asl | 2 +
3 files changed, 103 insertions(+)
diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl
new file mode 100644
index 0000000..a056bf5
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* CPU */
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 6000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/intel/kunimitsu/acpi_tables.c b/src/mainboard/intel/kunimitsu/acpi_tables.c
index f9eb7b0..640cd05 100644
--- a/src/mainboard/intel/kunimitsu/acpi_tables.c
+++ b/src/mainboard/intel/kunimitsu/acpi_tables.c
@@ -47,6 +47,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tmax = MAX_TEMPERATURE;
+ gnvs->dpte = 1;
}
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl
index 6ac0be4..f9d67af 100644
--- a/src/mainboard/intel/kunimitsu/dsdt.asl
+++ b/src/mainboard/intel/kunimitsu/dsdt.asl
@@ -43,6 +43,8 @@ DefinitionBlock(
#include <soc/intel/skylake/acpi/systemagent.asl>
#include <soc/intel/skylake/acpi/pch.asl>
}
+ // Thermal handler
+ #include "acpi/dptf.asl"
}
// Chrome OS specific
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