[coreboot-gerrit] Patch set updated for coreboot: fsp1_1: remove duplicate mrc caching mechanism
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Sat Aug 29 03:41:43 CEST 2015
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11454
-gerrit
commit b3f339c8af7254d0db487765e06cbef7d42470ba
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Aug 27 22:49:03 2015 -0500
fsp1_1: remove duplicate mrc caching mechanism
For some reason fsp 1.1 has a duplicate mechanism for saving
mrc data as soc/intel/common. Defer to the common code as all
the existing users were already using the common code.
BUG=chrome-os-partner:44620
BRANCH=None
TEST=Built and booted glados. Suspended and resumed.
Change-Id: I951d47deb85445a5f010d23dfd11abb0b6f65e5e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Original-Commit-Id: 2138b6ff1517c440d24f72a5f399bd6cb6097274
Original-Change-Id: I06609c1435b06b1365b1762f83cfcba532eb8c7a
Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295236
Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
src/drivers/intel/fsp1_1/Kconfig | 51 ------
src/drivers/intel/fsp1_1/Makefile.inc | 16 --
src/drivers/intel/fsp1_1/fastboot_cache.c | 258 ------------------------------
src/drivers/intel/fsp1_1/fsp_util.h | 22 ---
src/drivers/intel/fsp1_1/hob.c | 96 +----------
5 files changed, 1 insertion(+), 442 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 33283db..42c42c0 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -58,15 +58,6 @@ config CPU_MICROCODE_CBFS_LOC
The location (base address) in CBFS that contains the microcode update
binary.
-config ENABLE_MRC_CACHE
- bool
- default y if HAVE_ACPI_RESUME
- default n
- help
- Enabling this feature will cause MRC data to be cached in NV storage.
- This can either be used for fast boot, or just because the FSP wants
- it to be saved.
-
config FSP_FILE
string "Intel FSP binary path and filename"
help
@@ -96,48 +87,6 @@ config FSP_LOC
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
-config MRC_CACHE_FILE
- string "File containing the cached MRC values"
- help
- The path and filename of the cached MRC values.
-
-config MRC_CACHE_LOC
- hex "Fast Boot Data Cache location in CBFS"
- default 0xfff50000
- depends on ENABLE_MRC_CACHE
- help
- The location in CBFS for the MRC data to be cached.
-
- WARNING: This should be on a sector boundary of the BIOS ROM chip
- and nothing else should be included in that sector, or IT WILL BE
- ERASED.
-
-config MRC_CACHE_SIZE
- hex "Fast Boot Data Cache Size"
- default 0x10000
- depends on ENABLE_MRC_CACHE
- help
- This is the amount of space in NV storage that is reserved for the
- fast boot data cache storage.
-
- WARNING: Because this area will be erased and re-written, the size
- should be a full sector of the flash ROM chip and nothing else should
- be included in CBFS in any sector that the fast boot cache data is in.
-
-config VIRTUAL_ROM_SIZE
- hex "Virtual ROM Size"
- default ROM_SIZE
- depends on ENABLE_MRC_CACHE
- help
- This is used to calculate the offset of the MRC data cache in NV
- Storage for fast boot. If in doubt, leave this set to the default
- which sets the virtual size equal to the ROM size.
-
- Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
- loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
- the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
- size is 16 MB.
-
endif #HAVE_FSP_BIN
config CACHE_ROM_SIZE_OVERRIDE
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 6c0b280..05dbfe5 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -18,12 +18,10 @@
# Foundation, Inc.
#
-romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
romstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
romstage-y += fsp_util.c
romstage-y += hob.c
-ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
@@ -47,17 +45,3 @@ fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
fsp.bin-position := $(CONFIG_FSP_LOC)
fsp.bin-type := fsp
endif
-
-
-# Create and add the MRC cache to the cbfs image
-ifeq ($(CONFIG_ENABLE_MRC_CACHE_FILE),y)
-$(obj)/mrc.cache:
- dd if=/dev/zero count=1 \
- bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \
- tr '\000' '\377' > $@
-
-cbfs-files-y += mrc.cache
-mrc.cache-file := $(call strip_quotes,$(CONFIG_MRC_CACHE_FILE))
-mrc.cache-position := $(CONFIG_MRC_CACHE_LOC)
-mrc.cache-type := mrc_cache
-endif
diff --git a/src/drivers/intel/fsp1_1/fastboot_cache.c b/src/drivers/intel/fsp1_1/fastboot_cache.c
deleted file mode 100644
index 9aa8a64..0000000
--- a/src/drivers/intel/fsp1_1/fastboot_cache.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "fsp_util.h"
-#include <ip_checksum.h>
-#include <lib.h> // hexdump
-#include <spi_flash.h>
-#include <string.h>
-
-#ifndef CONFIG_VIRTUAL_ROM_SIZE
-#error "CONFIG_VIRTUAL_ROM_SIZE must be set."
-#endif
-
-/* convert a pointer to flash area into the offset inside the flash */
-static inline u32 to_flash_offset(void *p)
-{
- return (u32)p + CONFIG_VIRTUAL_ROM_SIZE;
-}
-
-static struct mrc_data_container *next_mrc_block(
- struct mrc_data_container *mrc_cache)
-{
- /* MRC data blocks are aligned within the region */
- u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size;
- if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
- mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
- mrc_size += MRC_DATA_ALIGN;
- }
-
- u8 *region_ptr = (u8 *)mrc_cache;
- region_ptr += mrc_size;
- return (struct mrc_data_container *)region_ptr;
-}
-
-static int is_mrc_cache(struct mrc_data_container *mrc_cache)
-{
- return (!!mrc_cache)
- && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE);
-}
-
-static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
-{
- size_t region_size;
- *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
- CBFS_TYPE_MRC_CACHE,
- ®ion_size);
-
- return region_size;
-}
-
-/*
- * Find the largest index block in the MRC cache. Return NULL if none is
- * found.
- */
-static struct mrc_data_container *find_current_mrc_cache_local
- (struct mrc_data_container *mrc_cache, u32 region_size)
-{
- u32 region_end;
- u32 entry_id = 0;
- struct mrc_data_container *mrc_next = mrc_cache;
-
- region_end = (u32) mrc_cache + region_size;
-
- /* Search for the last filled entry in the region */
- while (is_mrc_cache(mrc_next)) {
- entry_id++;
- mrc_cache = mrc_next;
- mrc_next = next_mrc_block(mrc_next);
- if ((u32)mrc_next >= region_end) {
- /* Stay in the MRC data region */
- break;
- }
- }
-
- if (entry_id == 0) {
- printk(BIOS_ERR, "%s: No valid fast boot cache found.\n",
- __func__);
- return NULL;
- }
-
- /* Verify checksum */
- if (mrc_cache->mrc_checksum !=
- compute_ip_checksum(mrc_cache->mrc_data,
- mrc_cache->mrc_data_size)) {
- printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n",
- __func__);
- return NULL;
- }
-
- printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__,
- entry_id - 1);
-
- return mrc_cache;
-}
-
-/* SPI code needs malloc/free.
- * Also unknown if writing flash from XIP-flash code is a good idea
- */
-#if ENV_RAMSTAGE
-/* find the first empty block in the MRC cache area.
- * If there's none, return NULL.
- *
- * @mrc_cache_base - base address of the MRC cache area
- * @mrc_cache - current entry (for which we need to find next)
- * @region_size - total size of the MRC cache area
- */
-static struct mrc_data_container *find_next_mrc_cache
- (struct mrc_data_container *mrc_cache_base,
- struct mrc_data_container *mrc_cache,
- u32 region_size)
-{
- u32 region_end = (u32) mrc_cache_base + region_size;
- u32 mrc_data_size = mrc_cache->mrc_data_size;
-
- mrc_cache = next_mrc_block(mrc_cache);
- if (((u32)mrc_cache + mrc_data_size) >= region_end) {
- /* Crossed the boundary */
- mrc_cache = NULL;
- printk(BIOS_DEBUG, "%s: no available entries found\n",
- __func__);
- } else {
- printk(BIOS_DEBUG,
- "%s: picked next entry from cache block at %p\n",
- __func__, mrc_cache);
- }
-
- return mrc_cache;
-}
-
-void update_mrc_cache(void *unused)
-{
- printk(BIOS_DEBUG, "Updating fast boot cache data.\n");
- struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
- struct mrc_data_container *cache, *cache_base;
- u32 cache_size;
-
- if (!current) {
- printk(BIOS_ERR, "No fast boot cache in cbmem. Can't update flash.\n");
- return;
- }
- if (current->mrc_data_size == -1) {
- printk(BIOS_ERR, "Fast boot cache data in cbmem invalid.\n");
- return;
- }
-
- cache_base = NULL;
- cache_size = get_mrc_cache_region(&cache_base);
- if (cache_base == NULL) {
- printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
- __func__);
- return;
- }
-
- /*
- * we need to:
- * 0. compare MRC data to last mrc-cache block (exit if same)
- */
- cache = find_current_mrc_cache_local(cache_base, cache_size);
-
- if (cache && (cache->mrc_data_size == current->mrc_data_size) &&
- (memcmp(cache, current, cache->mrc_data_size) == 0)) {
- printk(BIOS_DEBUG,
- "MRC data in flash is up to date. No update.\n");
- return;
- }
-
- /* 1. use spi_flash_probe() to find the flash, then... */
- spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0);
- if (!flash) {
- printk(BIOS_DEBUG, "Could not find SPI device\n");
- return;
- }
-
- /* 2. look up the first unused block */
- if (cache)
- cache = find_next_mrc_cache(cache_base, cache, cache_size);
-
- /*
- * 3. if no such place exists, erase entire mrc-cache range & use
- * block 0. First time around the erase is not needed, but this is a
- * small overhead for simpler code.
- */
- if (!cache) {
- printk(BIOS_DEBUG,
- "Need to erase the MRC cache region of %d bytes at %p\n",
- cache_size, cache_base);
-
- flash->erase(flash, to_flash_offset(cache_base), cache_size);
-
- /* we will start at the beginning again */
- cache = cache_base;
- }
- /* 4. write mrc data with flash->write() */
- printk(BIOS_DEBUG, "Write MRC cache update to flash at %p\n",
- cache);
- flash->write(flash, to_flash_offset(cache),
- current->mrc_data_size + sizeof(*current), current);
-}
-
-#endif /* ENV_RAMSTAGE */
-
-void *find_and_set_fastboot_cache(void)
-{
- struct mrc_data_container *mrc_cache = NULL;
- mrc_cache = find_current_mrc_cache();
- if ((mrc_cache == NULL) ||
- (mrc_cache->mrc_data_size == -1UL)) {
- printk(BIOS_DEBUG, "FSP MRC cache not present.\n");
- return NULL;
- }
- printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache);
- printk(BIOS_SPEW, "Saved MRC data:\n");
- hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data,
- mrc_cache->mrc_data_size);
- return (void *) mrc_cache->mrc_data;
-}
-
-struct mrc_data_container *find_current_mrc_cache(void)
-{
- struct mrc_data_container *cache_base;
- u32 cache_size;
-
- cache_base = NULL;
- cache_size = get_mrc_cache_region(&cache_base);
- if (cache_base == NULL) {
- printk(BIOS_ERR, "%s: could not find fast boot cache area\n",
- __func__);
- return NULL;
- }
-
- /*
- * we need to:
- * 0. compare MRC data to last mrc-cache block (exit if same)
- */
- return find_current_mrc_cache_local(cache_base, cache_size);
-}
diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h
index fba9116..8f6f77a 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.h
+++ b/src/drivers/intel/fsp1_1/fsp_util.h
@@ -41,11 +41,6 @@
/* Include the EDK2 headers */
#include <soc/chipset_fsp_util.h>
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-int save_mrc_data(void *hob_start);
-void * find_and_set_fastboot_cache(void);
-#endif
-
/* find_fsp() should only be called from assembly code. */
FSP_INFO_HEADER *find_fsp(void);
/* Set FSP's runtime information. */
@@ -86,23 +81,6 @@ int fsp_relocate(struct prog *fsp_relocd, const struct region_device *fsp_src);
#define EFI_HOB_TYPE_HANDOFF 0x0001
#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
-
-struct mrc_data_container {
- u32 mrc_signature; // "MRCD"
- u32 mrc_data_size; // Actual total size of this structure
- u32 mrc_checksum; // IP style checksum
- u32 reserved; // For header alignment
- u8 mrc_data[0]; // Variable size, platform/run time dependent.
-} __attribute__ ((packed));
-
-struct mrc_data_container *find_current_mrc_cache(void);
-void update_mrc_cache(void *unused);
-
-#endif /* CONFIG_ENABLE_MRC_CACHE */
-
/* The offset in bytes from the start of the info structure */
#define FSP_IMAGE_SIG_LOC 0
#define FSP_IMAGE_ID_LOC 16
diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c
index 6cc09fb..edce61c 100644
--- a/src/drivers/intel/fsp1_1/hob.c
+++ b/src/drivers/intel/fsp1_1/hob.c
@@ -27,6 +27,7 @@
#include <ip_checksum.h>
#include <lib.h> // hexdump
#include <string.h>
+#include <soc/intel/common/mrc_cache.h>
/*
* Reads a 64-bit value from memory that may be unaligned.
@@ -401,98 +402,3 @@ void print_hob_type_structure(u16 hob_type, void *hob_list_ptr)
} while (!last_hob);
printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
}
-
-#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
-/*
- * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
- */
-int save_mrc_data(void *hob_start)
-{
- u32 *mrc_hob;
- u32 *mrc_hob_data;
- u32 mrc_hob_size;
- struct mrc_data_container *mrc_data;
- int output_len;
- const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
-
- mrc_hob = get_next_guid_hob(&mrc_guid, hob_start);
- if (mrc_hob == NULL) {
- printk(BIOS_DEBUG,
- "Memory Configure Data Hob is not present\n");
- return 0;
- }
-
- mrc_hob_data = GET_GUID_HOB_DATA(mrc_hob);
- mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob);
-
- printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n",
- (void *)mrc_hob_data, mrc_hob_size);
-
- output_len = ALIGN(mrc_hob_size, 16);
-
- /* Save the MRC S3/fast boot/ADR restore data to cbmem */
- mrc_data = cbmem_add(CBMEM_ID_MRCDATA,
- output_len + sizeof(struct mrc_data_container));
-
- /* Just return if there was a problem with getting CBMEM */
- if (mrc_data == NULL) {
- printk(BIOS_WARNING,
- "CBMEM was not available to save the fast boot cache data.\n");
- return 0;
- }
-
- printk(BIOS_DEBUG,
- "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n",
- (void *)mrc_hob_data, mrc_data, output_len);
-
- mrc_data->mrc_signature = MRC_DATA_SIGNATURE;
- mrc_data->mrc_data_size = output_len;
- mrc_data->reserved = 0;
- memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size);
-
- /* Zero the unused space in aligned buffer. */
- if (output_len > mrc_hob_size)
- memset((mrc_data->mrc_data + mrc_hob_size), 0,
- output_len - mrc_hob_size);
-
- mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data,
- mrc_data->mrc_data_size);
-
-#if IS_ENABLED(CONFIG_DISPLAY_FAST_BOOT_DATA)
- printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n");
- hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len);
-#endif
- return 1;
-}
-
-void __attribute__ ((weak)) update_mrc_cache(void *unused)
-{
- printk(BIOS_ERR, "Add routine %s to save the MRC data.\n", __func__);
-}
-#endif /* CONFIG_ENABLE_MRC_CACHE */
-
-#if ENV_RAMSTAGE
-
-static void find_fsp_hob_update_mrc(void *unused)
-{
- void *hob_list_ptr;
-
- /* 0x0000: Print all types */
- hob_list_ptr = get_hob_list();
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- print_hob_type_structure(0x000, hob_list_ptr);
-#endif
-
- #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
- if (save_mrc_data(hob_list_ptr))
- update_mrc_cache(NULL);
- else
- printk(BIOS_DEBUG, "Not updating MRC data in flash.\n");
- #endif
-}
-
-/* Update the MRC/fast boot cache as part of the late table writing stage */
-BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
- find_fsp_hob_update_mrc, NULL);
-
-#endif /* ENV_RAMSTAGE */
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