[coreboot-gerrit] New patch to review for coreboot: amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Fri Dec 11 20:02:49 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12712
-gerrit
commit 18f5fbf3f4c1305dcbca9863ed322828babc84b5
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Fri Dec 11 12:58:07 2015 -0600
amd/[nb/fam10|sb/sr5650]: Minor cosmetic changes
Change-Id: Ia9cb4fe4f46327e38648f89da0ffce647fb118d3
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdfam10/northbridge.c | 20 ++++++++++----------
src/southbridge/amd/sr5650/ht.c | 6 +++---
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index c8bf8fa..336bf60 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -737,16 +737,16 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
-#if CONFIG_MMCONF_SUPPORT
- struct resource *res = new_resource(dev, 0xc0010058);
- res->base = CONFIG_MMCONF_BASE_ADDRESS;
- res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
- res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-
- /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
- ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
-#endif
+ if (IS_ENABLED(CONFIG_MMCONF_SUPPORT) && !IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
+ struct resource *res = new_resource(dev, 0xc0010058);
+ res->base = CONFIG_MMCONF_BASE_ADDRESS;
+ res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
+ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
+ }
if (is_fam15h()) {
enable_cc6 = 0;
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index 6119985..d3d72a2 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -157,8 +157,8 @@ static void sr5690_read_resource(struct device *dev)
pci_dev_read_resources(dev);
/* rpr6.2.(1). Write the Base Address Register (BAR) */
- pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
- pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
+ pci_write_config32(dev, 0xf8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
+ pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */
compact_resources(dev);
}
@@ -166,7 +166,7 @@ static void sr5690_read_resource(struct device *dev)
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
static void sr5690_set_resources(struct device *dev)
{
- pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
+ pci_write_config32(dev, 0xf8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
pci_dev_set_resources(dev);
}
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