[coreboot-gerrit] New patch to review for coreboot: Braswell: Disable SD card detect simulation in FSP
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed Dec 16 04:17:15 CET 2015
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12742
-gerrit
commit 7544c5259e1d979f06ee8df419957959a2561a22
Author: Divya Sasidharan <divya.s.sasidharan at intel.com>
Date: Wed Oct 28 15:02:35 2015 -0700
Braswell: Disable SD card detect simulation in FSP
Debounce for SD card detect takes a long time and thus affects boot time.
Disabling SD card detect simulation in FSP through UPD
Reviewed-on: https://chromium-review.googlesource.com/311850
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Commit-Queue: Hannah Williams <hannah.williams at intel.com>
Tested-by: Hannah Williams <hannah.williams at intel.com>
Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71
Signed-off-by: Divya Sasidharan <divya.s.sasidharan at intel.com>
---
src/mainboard/google/cyan/devicetree.cb | 1 +
src/mainboard/intel/strago/devicetree.cb | 1 +
src/soc/intel/braswell/chip.c | 3 +++
src/soc/intel/braswell/chip.h | 1 +
4 files changed, 6 insertions(+)
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index c36ae3d..6ba7b7c 100755
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -70,6 +70,7 @@ chip soc/intel/braswell
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
+ register "PcdSdDetectChk" = "0" # Disable SD card detect
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index bcf92f1..5250415 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -70,6 +70,7 @@ chip soc/intel/braswell
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
+ register "PcdSdDetectChk" = "0" # Disable SD card detect
# LPE audio codec settings
register "lpe_codec_clk_freq" = "25" # 25MHz clock
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 6cf3e8a..1e04faa 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -152,6 +152,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->PMIC_I2CBus = config->PMIC_I2CBus;
params->ISPEnable = config->ISPEnable;
params->ISPPciDevConfig = config->ISPPciDevConfig;
+ params->PcdSdDetectChk = config->PcdSdDetectChk;
}
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
@@ -312,6 +313,8 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
old->ISPEnable, new->ISPEnable);
fsp_display_upd_value("ISPPciDevConfig", 1,
old->ISPPciDevConfig, new->ISPPciDevConfig);
+ soc_display_upd_value("PcdSdDetectChk", 1,
+ old->PcdSdDetectChk, new->PcdSdDetectChk);
}
/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 0f3c1d0..acbfee0 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -135,6 +135,7 @@ struct soc_intel_braswell_config {
UINT8 PMIC_I2CBus;
UINT8 ISPEnable;
UINT8 ISPPciDevConfig;
+ UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/
};
extern struct chip_operations soc_intel_braswell_ops;
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