[coreboot-gerrit] Patch set updated for coreboot: Braswell: Fix DSP clock
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed Dec 16 19:26:03 CET 2015
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12732
-gerrit
commit 73853464597b755df56a7cfb6e4a572dee17aaa6
Author: fdurairx <felixx.durairaj at intel.com>
Date: Fri Aug 21 15:36:53 2015 -0700
Braswell: Fix DSP clock
The codec clock frequency was incorectlty set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.
Reviewed-on: https://chromium-review.googlesource.com/295768
Commit-Queue: Hannah Williams <hannah.williams at intel.com>
Tested-by: Hannah Williams <hannah.williams at intel.com>
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj at intel.com>
---
src/mainboard/google/cyan/devicetree.cb | 2 +-
src/soc/intel/braswell/chip.h | 2 +-
src/soc/intel/braswell/include/soc/pm.h | 4 ++--
src/soc/intel/braswell/lpe.c | 18 ++++++++++--------
4 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb
index c36ae3d..208e05a 100755
--- a/src/mainboard/google/cyan/devicetree.cb
+++ b/src/mainboard/google/cyan/devicetree.cb
@@ -72,7 +72,7 @@ chip soc/intel/braswell
register "ISPPciDevConfig" = "3"
# LPE audio codec settings
- register "lpe_codec_clk_freq" = "25" # 25MHz clock
+ register "lpe_codec_clk_src" = '0' # 19.2MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# Enable devices in ACPI mode
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 0f3c1d0..51c02dd 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -41,7 +41,7 @@ struct soc_intel_braswell_config {
int disable_slp_x_stretch_sus_fail;
/* LPE Audio Clock configuration. */
- int lpe_codec_clk_freq; /* 19 or 25 are valid. */
+ int lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */
int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
/* Native SD Card controller - override controller capabilities. */
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 9708b39..a4b2e2d 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -116,8 +116,8 @@
#define PLT_CLK_CTL_3 0x6c
#define PLT_CLK_CTL_4 0x70
#define PLT_CLK_CTL_5 0x74
-# define CLK_FREQ_25MHZ (0x0 << 2)
-# define CLK_FREQ_19P2MHZ (0x1 << 2)
+# define CLK_SRC_XTAL (0x0 << 2)
+# define CLK_SRC_PLL (0x1 << 2)
# define CLK_CTL_D3_LPE (0x0 << 0)
# define CLK_CTL_ON (0x1 << 0)
# define CLK_CTL_OFF (0x2 << 0)
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index a1a7c64..30b87bd 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -96,17 +96,19 @@ static void setup_codec_clock(device_t dev)
const char *freq_str;
config = dev->chip_info;
- switch (config->lpe_codec_clk_freq) {
- case 19:
- freq_str = "19.2";
- reg = CLK_FREQ_19P2MHZ;
+ switch (config->lpe_codec_clk_src) {
+ case 0:
+ /* XTAL driven bit2=0*/
+ freq_str = "19.2Mhz External Crystal";
+ reg = CLK_SRC_XTAL;
break;
- case 25:
- freq_str = "25";
- reg = CLK_FREQ_25MHZ;
+ case 1:
+ /* PLL driven bit2=1*/
+ freq_str = "19.2Mhz PLL";
+ reg = CLK_SRC_PLL;
break;
default:
- printk(BIOS_DEBUG, "LPE codec clock not required.\n");
+ printk(BIOS_DEBUG, "LPE codec clock default.\n");
return;
}
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