[coreboot-gerrit] New patch to review for coreboot: Strago: Enable CA Mirror
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Wed Dec 16 21:48:44 CET 2015
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12749
-gerrit
commit fd6335183bd36a36b62e90f699d94281fd7e3c38
Author: Shobhit Srivastava <shobhit.srivastava at intel.com>
Date: Fri Oct 9 17:05:16 2015 +0530
Strago: Enable CA Mirror
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is enabled
on this board
Reviewed-on: https://chromium-review.googlesource.com/309190
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: Hannah Williams <hannah.williams at intel.com>
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
Commit-Queue: Hannah Williams <hannah.williams at intel.com>
Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Signed-off-by: Divya Sasidharan <divya.s.sasidharan at intel.com>
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/mainboard/intel/strago/devicetree.cb | 1 +
src/soc/intel/braswell/chip.h | 1 +
src/soc/intel/braswell/romstage/romstage.c | 1 +
.../intel/fsp/fsp1_1/braswell/FspUpdVpd.h | 33 ++++++++++++----------
4 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index bcf92f1..bf2170e 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -13,6 +13,7 @@ chip soc/intel/braswell
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
+ register "PcdCaMirrorEn" = "1"
############################################################
# Set the parameters for SiliconInit
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 0f3c1d0..11c14b1 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -71,6 +71,7 @@ struct soc_intel_braswell_config {
UINT8 PcdGttSize;
UINT8 PcdLegacySegDecode;
UINT8 PcdDvfsEnable;
+ UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */
/*
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2581583..028469a 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -212,6 +212,7 @@ void soc_memory_init_params(struct romstage_params *params,
upd->PcdGttSize = config->PcdGttSize;
upd->PcdLegacySegDecode = config->PcdLegacySegDecode;
upd->PcdDvfsEnable = config->PcdDvfsEnable;
+ upd->PcdCaMirrorEn = config->PcdCaMirrorEn;
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
index 9b9df0e..da41971 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h
@@ -188,8 +188,13 @@ typedef struct {
**/
UINT8 PcdMemoryTypeEnable;
/** Offset 0x0042
+ CaMirrorEn
+ To Enable/Disable CaMirrorEn
**/
- UINT8 ReservedMemoryInitUpd[190];
+ UINT8 PcdCaMirrorEn;
+/** Offset 0x0043
+**/
+ UINT8 ReservedMemoryInitUpd[189];
} MEMORY_INIT_UPD;
typedef struct {
@@ -436,8 +441,18 @@ typedef struct {
**/
UINT8 PcdTurboMode;
/** Offset 0x0161
+ Pnp Setting Type
+ Select Pnp type
+**/
+ UINT8 PcdPnpSettings;
+/** Offset 0x0162
+ SdDetectChk
+ Check for Sd card detect
**/
- UINT8 ReservedSiliconInitUpd[413];
+ UINT8 PcdSdDetectChk;
+/** Offset 0x0163
+**/
+ UINT8 ReservedSiliconInitUpd[411];
} SILICON_INIT_UPD;
#define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */
@@ -472,16 +487,10 @@ typedef struct _UPD_DATA_REGION {
/** Offset 0x02FE
**/
UINT16 PcdRegionTerminator;
-/** Offset 0x0300
-**/
- UINT8 UnusedUpdSpace4[2123];
-/** Offset 0x0B4B
-**/
- UINT8 PcdPaddingSpace;
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
-#define FSP_IMAGE_REV 0x01010100
+#define FSP_IMAGE_REV 0x01010400
typedef struct _VPD_DATA_REGION {
/** Offset 0x0000
@@ -494,12 +503,6 @@ typedef struct _VPD_DATA_REGION {
/** Offset 0x000C
**/
UINT32 PcdUpdRegionOffset;
-/** Offset 0x0010
-**/
- UINT8 UnusedVpdSpace0[20];
-/** Offset 0x0024
-**/
- UINT8 PcdEnableSecureBoot;
} VPD_DATA_REGION;
#pragma pack(pop)
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