[coreboot-gerrit] New patch to review for coreboot: b6c8f05 lenovo/t(2, 3)0(s), x(2, 3)0: fix smi gpe pin config
Nicolas Reinecke (nr@das-labor.org)
gerrit at coreboot.org
Thu Feb 5 01:35:45 CET 2015
Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8358
-gerrit
commit b6c8f05bebc5fc8ce5cc678db8abad446ab17d20
Author: Nicolas Reinecke <nr at das-labor.org>
Date: Sun Feb 1 02:53:35 2015 +0100
lenovo/t(2,3)0(s),x(2,3)0: fix smi gpe pin config
Verified with schematics.
Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c
Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
---
src/mainboard/lenovo/t420s/devicetree.cb | 2 +-
src/mainboard/lenovo/t420s/smihandler.c | 19 +++++++++++--------
src/mainboard/lenovo/t520/devicetree.cb | 2 +-
src/mainboard/lenovo/t520/smihandler.c | 19 +++++++++++--------
src/mainboard/lenovo/t530/devicetree.cb | 2 +-
src/mainboard/lenovo/t530/smihandler.c | 19 +++++++++++--------
src/mainboard/lenovo/x220/devicetree.cb | 2 +-
src/mainboard/lenovo/x220/smihandler.c | 19 +++++++++++--------
src/mainboard/lenovo/x230/devicetree.cb | 2 +-
src/mainboard/lenovo/x230/smihandler.c | 19 +++++++++++--------
10 files changed, 60 insertions(+), 45 deletions(-)
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index 990b576..7fd6a53 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
- register "gpi8_routing" = "2"
+ register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)
register "sata_port_map" = "0x17"
diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c
index 6c80573..27a33cf 100644
--- a/src/mainboard/lenovo/t420s/smihandler.c
+++ b/src/mainboard/lenovo/t420s/smihandler.c
@@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (gpi_sts & (1 << 12))
+ if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
@@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ /* route EC_SCI to SCI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ /* route EC_SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
@@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+ outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << 26);
- gpe_rout |= (2 << 26);
+ gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
+ gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index d2a4d6b..bf575d8 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
- register "gpi8_routing" = "2"
+ register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
register "sata_port_map" = "0x1f"
diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c
index bb3ad78..479ce0a 100644
--- a/src/mainboard/lenovo/t520/smihandler.c
+++ b/src/mainboard/lenovo/t520/smihandler.c
@@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -103,7 +106,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (gpi_sts & (1 << 12))
+ if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
@@ -124,8 +127,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ /* route EC_SCI to SCI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -137,8 +140,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ /* route EC_SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
@@ -178,11 +181,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+ outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << 26);
- gpe_rout |= (2 << 26);
+ gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
+ gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb
index c44f927..6b769b0 100644
--- a/src/mainboard/lenovo/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/devicetree.cb
@@ -50,7 +50,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
- register "gpi8_routing" = "2"
+ register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
register "sata_port_map" = "0x3f"
diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c
index 6f6cca1..372f280 100644
--- a/src/mainboard/lenovo/t530/smihandler.c
+++ b/src/mainboard/lenovo/t530/smihandler.c
@@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (gpi_sts & (1 << 12))
+ if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
@@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ /* route EC_SCI to SCI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ /* route EC_SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
@@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+ outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << 26);
- gpe_rout |= (2 << 26);
+ gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
+ gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 982e30b..6eb3b15 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
- register "gpi8_routing" = "2"
+ register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
register "sata_port_map" = "0x7"
diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c
index 6f6cca1..372f280 100644
--- a/src/mainboard/lenovo/x220/smihandler.c
+++ b/src/mainboard/lenovo/x220/smihandler.c
@@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (gpi_sts & (1 << 12))
+ if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
@@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ /* route EC_SCI to SCI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ /* route EC_SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
@@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+ outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << 26);
- gpe_rout |= (2 << 26);
+ gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
+ gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 3a05b5a..08c937f 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0000"
register "gpi1_routing" = "2"
- register "gpi8_routing" = "2"
+ register "gpi13_routing" = "2"
# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
register "sata_port_map" = "0x7"
diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c
index 6f6cca1..372f280 100644
--- a/src/mainboard/lenovo/x230/smihandler.c
+++ b/src/mainboard/lenovo/x230/smihandler.c
@@ -33,6 +33,9 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -108,7 +111,7 @@ static void mainboard_smi_handle_ec_sci(void)
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (gpi_sts & (1 << 12))
+ if (gpi_sts & (1 << GPE_EC_SCI))
mainboard_smi_handle_ec_sci();
}
@@ -129,8 +132,8 @@ int mainboard_smi_apmc(u8 data)
case APM_CNT_ACPI_ENABLE:
/* use 0x1600/0x1604 to prevent races with userspace */
ec_set_ports(0x1604, 0x1600);
- /* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ /* route EC_SCI to SCI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -142,8 +145,8 @@ int mainboard_smi_apmc(u8 data)
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
provide a EC query function */
ec_set_ports(0x66, 0x62);
- /* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000,
+ /* route EC_SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
@@ -183,11 +186,11 @@ void mainboard_smi_sleep(u8 slp_typ)
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
/* Enable EC WAKE GPE. */
- outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN);
+ outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
/* Redirect EC WAKE GPE to SCI. */
- gpe_rout &= ~(3 << 26);
- gpe_rout |= (2 << 26);
+ gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
+ gpe_rout |= (2 << (GPE_EC_WAKE * 2));
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
}
}
More information about the coreboot-gerrit
mailing list