[coreboot-gerrit] New patch to review for coreboot: e3bd569 pcengines/apu1: Fix 0:15.x PCIe root ports
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sat Feb 7 19:03:46 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8388
-gerrit
commit e3bd56952de7d028c388b8b8ed35e26ea80d6327
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sat Jan 17 18:08:40 2015 +0200
pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.
Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.
Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/mainboard/pcengines/apu1/devicetree.cb | 2 +-
src/mainboard/pcengines/apu1/platform_cfg.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 0f72fb6..4209ba6 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -83,7 +83,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
- register "gpp_configuration" = "0"
+ register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h
index 2efe905..6d40663 100644
--- a/src/mainboard/pcengines/apu1/platform_cfg.h
+++ b/src/mainboard/pcengines/apu1/platform_cfg.h
@@ -186,7 +186,7 @@
* GPP_CFGMODE_X2110
* GPP_CFGMODE_X1111
*/
-#define GPP_CFGMODE GPP_CFGMODE_X4000
+#define GPP_CFGMODE GPP_CFGMODE_X1111
/**
* @def NB_SB_GEN2
@@ -207,7 +207,7 @@
* TRUE - ports visible always, even port empty
* FALSE - ports invisible if port empty
*/
-#define SB_GPP_UNHIDE_PORTS TRUE
+#define SB_GPP_UNHIDE_PORTS FALSE
/**
* @def GEC_CONFIG
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