[coreboot-gerrit] New patch to review for coreboot: 982a45d intel/fsp_baytrail: Add Android boot support for BayTrail SoCs
Brenton Dong (brenton.m.dong@intel.com)
gerrit at coreboot.org
Tue Feb 10 22:11:12 CET 2015
Brenton Dong (brenton.m.dong at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8407
-gerrit
commit 982a45dcc35139ddb3492b6b7cf6a6db7beea3c2
Author: Brenton Dong <brenton.m.dong at intel.com>
Date: Tue Feb 10 09:00:25 2015 -0700
intel/fsp_baytrail: Add Android boot support for BayTrail SoCs
IRQ and GPIO routing needed to be added for Android.
Change-Id: I9286125736c2572205e64a464884ee935c483df2
Signed-off-by: Brenton Dong <brenton.m.dong at intel.com>
---
src/soc/intel/fsp_baytrail/acpi/gpio.asl | 213 +++++++++++++++++++-----------
src/soc/intel/fsp_baytrail/southcluster.c | 53 ++++++++
2 files changed, 191 insertions(+), 75 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/acpi/gpio.asl b/src/soc/intel/fsp_baytrail/acpi/gpio.asl
old mode 100644
new mode 100755
index f2618a8..bb07a76
--- a/src/soc/intel/fsp_baytrail/acpi/gpio.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/gpio.asl
@@ -22,89 +22,152 @@
#include <soc/intel/fsp_baytrail/baytrail/iomap.h>
#include <soc/intel/fsp_baytrail/baytrail/irq.h>
-/* SouthCluster GPIO */
-Device (GPSC)
-{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
- Name (_UID, 1)
+Name (GPBS, 0x0500)
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
- {
- GPIO_SC_IRQ
- }
- })
+/* SouthCluster GPIO */
+ Device (GPO0)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_HID, "INT33B2") // _HID: Hardware ID
+ Name (_CID, "INT33B2") // _CID: Compatible ID
+ Name (_DDN, "ValleyView General Purpose Input/Output (GPIO) controller") // _DDN: DOS Device Name
+ Name (_UID, One) // _UID: Unique ID
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED0C000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000031,
+ }
+ })
+ Return (RBUF)
+ }
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
- Return (^RBUF)
- }
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
- Method (_STA)
- {
- Return (0xF)
- }
-}
+ Name (AVBL, Zero)
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If (LEqual (Arg0, 0x08))
+ {
+ Store (Arg1, AVBL)
+ }
+ }
-/* NorthCluster GPIO */
-Device (GPNC)
-{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
- Name (_UID, 2)
+ OperationRegion (GPOP, SystemIO, GPBS, 0x50)
+ Field (GPOP, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x28),
+ , 21,
+ BTD3, 1,
+ Offset (0x48),
+ , 30,
+ SHD3, 1
+ }
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
- {
- GPIO_NC_IRQ
- }
- })
+ OperationRegion (GPO2, GeneralPurposeIo, Zero, 0x0C)
+ Field (GPO2, ByteAcc, NoLock, Preserve)
+ {
+ Connection (
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO0", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x005F
+ }
+ ),
+ SHS3, 1
+ }
+ }
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
- Return (^RBUF)
- }
+ Device (GPO1)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_HID, "INT33B2") // _HID: Hardware ID
+ Name (_CID, "INT33B2") // _CID: Compatible ID
+ Name (_DDN, "ValleyView GPNCORE controller") // _DDN: DOS Device Name
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED0D000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000030,
+ }
+ })
+ Return (RBUF)
+ }
- Method (_STA)
- {
- Return (0xF)
- }
-}
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+ }
-/* SUS GPIO */
-Device (GPSS)
-{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
- Name (_UID, 3)
+ Device (GPO2)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_HID, "INT33B2") // _HID: Hardware ID
+ Name (_CID, "INT33B2") // _CID: Compatible ID
+ Name (_DDN, "ValleyView GPSUS controller") // _DDN: DOS Device Name
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED0E000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
+ {
+ 0x00000032,
+ }
+ })
+ Return (RBUF)
+ }
- Name (RBUF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
- {
- GPIO_SUS_IRQ
- }
- })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
- Method (_CRS)
- {
- CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
- Return (^RBUF)
- }
+ Name (AVBL, Zero)
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If (LEqual (Arg0, 0x08))
+ {
+ Store (Arg1, AVBL)
+ }
+ }
- Method (_STA)
- {
- Return (0xF)
- }
-}
+ Name (GMOD, ResourceTemplate ()
+ {
+ GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
+ "\\_SB.GPO2", 0x00, ResourceConsumer, ,
+ )
+ { // Pin list
+ 0x0015
+ }
+ })
+ OperationRegion (GPOP, SystemIO, GPBS, 0x0100)
+ Field (GPOP, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x88),
+ , 20,
+ WFD3, 1
+ }
+ }
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
old mode 100644
new mode 100755
index d87935b..c0f16dd
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -50,6 +50,40 @@
typedef struct soc_intel_fsp_baytrail_config config_t;
+typedef struct {
+ uint8_t bus;
+ uint8_t dev;
+ uint8_t func;
+ uint8_t irq;
+} irq_tbl_t;
+
+static const irq_tbl_t soc_irq_tbl[] = {
+ /*Bus Dev Fun Irq*/
+ { 0, 2, 0, 7 }, /* DISPLAY */
+ { 0, 21, 0, 29 }, /* LPE Audio */
+ { 0, 24, 1, 32 }, /* I2C1 */
+ { 0, 24, 2, 33 }, /* I2C2 */
+ { 0, 24, 3, 34 }, /* I2C3 */
+ { 0, 24, 4, 35 }, /* I2C4 */
+ { 0, 24, 5, 36 }, /* I2C5 */
+ { 0, 24, 6, 37 }, /* I2C6 */
+ { 0, 24, 7, 38 }, /* I2C7 */
+ { 0, 30, 3, 39 }, /* HSUART1 */
+ { 0, 30, 4, 40 }, /* HSUART1 */
+ { 0, 30, 5, 41 }, /* SPI1 */
+ { 0, 30, 0, 42 }, /* LI01 DMA */
+ { 0, 24, 0, 43 }, /* LI02 DMA */
+ { 0, 23, 0, 44 }, /* MIPI-HSI */
+ { 0, 16, 0, 45 }, /* SDIO1/eMMC */
+ { 0, 17, 0, 46 }, /* SDIO2/SDIO */
+ { 0, 18, 0, 47 }, /* SDIO3/SD */
+ { 0, 29, 0, 11 }, /* USB */
+ { 0, 20, 0, 23 }, /* OTG */
+ { 0, 22, 0, 16 }, /* XHCI */
+ { 0, 26, 0, 23 }, /* SEC */
+ { 0, 27, 0, 22 } /* HD Audio */
+};
+
static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
{
@@ -156,6 +190,22 @@ static void sc_enable_serial_irqs(struct device *dev)
#endif /* DON'T SET UP IRQS */
}
+static uint8_t update_soc_irq (struct device *dev)
+{
+ int i;
+ uint8_t irq;
+
+ irq = PIRQ_PIC_IRQDISABLE;
+
+ for (i = 0; i < sizeof(soc_irq_tbl)/sizeof(soc_irq_tbl[0]); i++) {
+ if (PCI_DEVFN(soc_irq_tbl[i].dev, soc_irq_tbl[i].func) == dev->path.pci.devfn) {
+ irq = soc_irq_tbl[i].irq;
+ break;
+ }
+ }
+ return irq;
+}
+
/*
* Write PCI config space IRQ assignments. PCI devices have the INT_LINE
* (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
@@ -230,7 +280,10 @@ static void write_pci_config_irqs(void)
pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF;
/* Get the INT_LINE this device/function will use */
+ int_line = update_soc_irq (irq_dev);
+ if (int_line == PIRQ_PIC_IRQDISABLE) {
int_line = ir->pic[pirq];
+ }
if (int_line != PIRQ_PIC_IRQDISABLE) {
/* Set this IRQ to level triggered since it is used by a PCI device */
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