[coreboot-gerrit] New patch to review for coreboot: dbb9434 AMD K8: Move the test for connected HyperTransport link
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sat Feb 28 14:50:31 CET 2015
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8549
-gerrit
commit dbb943445e3851509299fdae05184cf737d40591
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Wed Feb 4 15:23:03 2015 +0200
AMD K8: Move the test for connected HyperTransport link
Change-Id: I7f8cbfcae7ec2a49e91ceda1eecdcf76b2137d8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/northbridge/amd/amdk8/northbridge.c | 32 +++++++++++++++++++-------------
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 29fa2a4..63f543e 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -79,6 +79,23 @@ static void f1_write_config32(unsigned reg, u32 value)
}
}
+static bool is_non_coherent_link(struct device *dev, struct bus *link)
+{
+ u32 link_type;
+ do {
+ link_type = pci_read_config32(dev, link->cap + 0x18);
+ } while (link_type & ConnectionPending);
+
+ if (!(link_type & LinkConnected))
+ return false;
+
+ do {
+ link_type = pci_read_config32(dev, link->cap + 0x18);
+ } while (!(link_type & InitComplete));
+
+ return !!(link_type & NonCoherent);
+}
+
static u32 amdk8_nodeid(device_t dev)
{
return (dev->path.pci.devfn >> 3) - 0x18;
@@ -87,8 +104,6 @@ static u32 amdk8_nodeid(device_t dev)
static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink,
u32 max)
{
-
- u32 link_type;
int i;
u32 busses, config_busses;
u32 free_reg, config_reg;
@@ -98,18 +113,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
u32 max_devfn;
link->cap = 0x80 + (link->link_num * 0x20);
- do {
- link_type = pci_read_config32(dev, link->cap + 0x18);
- } while(link_type & ConnectionPending);
- if (!(link_type & LinkConnected)) {
- return max;
- }
- do {
- link_type = pci_read_config32(dev, link->cap + 0x18);
- } while(!(link_type & InitComplete));
- if (!(link_type & NonCoherent)) {
+ if (!is_non_coherent_link(dev, link))
return max;
- }
+
/* See if there is an available configuration space mapping
* register in function 1.
*/
More information about the coreboot-gerrit
mailing list