[coreboot-gerrit] New patch to review for coreboot: 63fea40 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8560

-gerrit

commit 63fea407325beaa4364ae4a8a08c608433ade83f
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Feb 21 14:31:01 2015 +0200

    AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree
    
    When we want to scan the HT chain to southbridge first, we
    relocate it as the first item of dev->link_list of node 0.
    
    Change-Id: Ic73ba43aadb3c5e0c8d4b82ed7d41094692ea37f
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/northbridge/amd/amdfam10/northbridge.c | 46 +++++++++++++++++++++++-------
 src/northbridge/amd/amdk8/northbridge.c    | 46 +++++++++++++++++++++++-------
 2 files changed, 72 insertions(+), 20 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 8e6fe45..c96e4b0 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -246,6 +246,36 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
 		return max;
 }
 
+/* Do sb ht chain at first, in case s2885 put sb chain
+ * (8131/8111) on link2, but put 8151 on link0.
+ */
+static void relocate_sb_ht_chain(void)
+{
+	struct device *dev;
+	struct bus *link, *prev = NULL;
+	u8 sblink;
+
+	if (!CONFIG_SB_HT_CHAIN_ON_BUS0)
+		return;
+
+	dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	sblink = (pci_read_config32(dev, 0x64)>>8) & 7;
+	link = dev->link_list;
+
+	while (link) {
+		if (link->link_num == sblink) {
+			if (!prev)
+				return;
+			prev->next = link->next;
+			link->next = dev->link_list;
+			dev->link_list = link;
+			return;
+		}
+		prev = link;
+		link = link->next;
+	}
+}
+
 static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
 {
 	unsigned nodeid;
@@ -254,18 +284,8 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
 
 	nodeid = amdfam10_nodeid(dev);
 
-	/* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */
 	for (link = dev->link_list; link; link = link->next) {
 		bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
-		if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
-			max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max);
-	}
-
-	for (link = dev->link_list; link; link = link->next) {
-		bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
-		if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
-			continue;
-
 		max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max);
 	}
 	return max;
@@ -555,9 +575,15 @@ static const struct pci_driver mcf0_driver __pci_driver = {
 	.device = 0x1200,
 };
 
+static void amdfam10_nb_init(void *chip_info)
+{
+	relocate_sb_ht_chain();
+}
+
 struct chip_operations northbridge_amd_amdfam10_ops = {
 	CHIP_NAME("AMD FAM10 Northbridge")
 	.enable_dev = 0,
+	.init = amdfam10_nb_init,
 };
 
 static void amdfam10_domain_read_resources(device_t dev)
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 2adbccf..1a813e1 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -221,6 +221,36 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
 		return max;
 }
 
+/* Do sb ht chain at first, in case s2885 put sb chain
+ * (8131/8111) on link2, but put 8151 on link0.
+ */
+static void relocate_sb_ht_chain(void)
+{
+	struct device *dev;
+	struct bus *link, *prev = NULL;
+	u8 sblink;
+
+	if (!CONFIG_SB_HT_CHAIN_ON_BUS0)
+		return;
+
+	dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
+	link = dev->link_list;
+
+	while (link) {
+		if (link->link_num == sblink) {
+			if (!prev)
+				return;
+			prev->next = link->next;
+			link->next = dev->link_list;
+			dev->link_list = link;
+			return;
+		}
+		prev = link;
+		link = link->next;
+	}
+}
+
 static unsigned amdk8_scan_chains(device_t dev, unsigned max)
 {
 	unsigned nodeid;
@@ -231,18 +261,8 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max)
 	if (nodeid == 0)
 		sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
 
-	// do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
 	for (link = dev->link_list; link; link = link->next) {
 		bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
-		if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
-			max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max);
-	}
-
-	for (link = dev->link_list; link; link = link->next) {
-		bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
-		if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
-			continue;
-
 		max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max);
 	}
 	return max;
@@ -614,9 +634,15 @@ static const struct pci_driver mcf0_driver __pci_driver = {
 	.device = 0x1100,
 };
 
+static void amdk8_nb_init(void *chip_info)
+{
+	relocate_sb_ht_chain();
+}
+
 struct chip_operations northbridge_amd_amdk8_ops = {
 	CHIP_NAME("AMD K8 Northbridge")
 	.enable_dev = 0,
+	.init = amdk8_nb_init,
 };
 
 static void amdk8_domain_read_resources(device_t dev)