[coreboot-gerrit] New patch to review for coreboot: f192797 intel/cpu/model_2065x|nehalem: remove MSR_PP0/MSR_PP1 its not supported by this cpu
Alexander Couzens (lynxis@fe80.eu)
gerrit at coreboot.org
Wed Jan 28 03:01:54 CET 2015
Alexander Couzens (lynxis at fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8295
-gerrit
commit f1927977893c03954f1e54f08b3b79ea7edd7964
Author: Alexander Couzens <lynxis at fe80.eu>
Date: Wed Jan 28 03:00:42 2015 +0100
intel/cpu/model_2065x|nehalem: remove MSR_PP0/MSR_PP1 its not supported by this cpu
It seems to be a relict when this cpu support was backported from sandybridge
Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf
Signed-off-by: Alexander Couzens <lynxis at fe80.eu>
---
src/cpu/intel/model_2065x/finalize.c | 17 -----------------
src/cpu/intel/model_2065x/model_2065x.h | 10 ----------
2 files changed, 27 deletions(-)
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index bb4c347..94a02c0 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -52,23 +52,6 @@ void intel_model_2065x_finalize_smm(void)
if (cpuid_ecx(1) & (1 << 25))
msr_set_bit(MSR_FEATURE_CONFIG, 0);
-#ifdef LOCK_POWER_CONTROL_REGISTERS
- /*
- * Lock the power control registers.
- *
- * These registers can be left unlocked if modifying power
- * limits from the OS is desirable. Modifying power limits
- * from the OS can be especially useful for experimentation
- * during early phases of system bringup while the thermal
- * power envelope is being proven.
- */
-
- msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
- msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
- msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
- msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
- msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
-#endif
/* Lock TM interupts - route thermal events to all processors */
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index f9dc7e8..454f7be 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -74,16 +74,6 @@
#define PKG_POWER_LIMIT_TIME_SHIFT 17
#define PKG_POWER_LIMIT_TIME_MASK 0x7f
-#define MSR_PP0_CURRENT_CONFIG 0x601
-#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
-#define MSR_PP1_CURRENT_CONFIG 0x602
-#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
-#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
-#define MSR_PKG_POWER_SKU_UNIT 0x606
-#define MSR_PKG_POWER_SKU 0x614
-#define MSR_PP0_POWER_LIMIT 0x638
-#define MSR_PP1_POWER_LIMIT 0x640
-
#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
#define MSR_CONFIG_TDP_NOMINAL 0x648
#define MSR_CONFIG_TDP_LEVEL1 0x649
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