[coreboot-gerrit] New patch to review for coreboot: beecee7 pistashio: increase romstage size
Ionela Voinescu (ionela.voinescu@imgtec.com)
gerrit at coreboot.org
Mon Jun 8 00:50:40 CEST 2015
Ionela Voinescu (ionela.voinescu at imgtec.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10457
-gerrit
commit beecee73b7ad5e36e6ee73ffc4450480b121666d
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Sun Jun 7 23:07:16 2015 +0100
pistashio: increase romstage size
This change is necessary to support future additions to romstage.
Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146
Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 326a26b..b36d47e 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -38,8 +38,8 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
- ROMSTAGE(0x1a005000, 36K)
- PRERAM_CBFS_CACHE(0x1a00e000, 72K)
+ ROMSTAGE(0x1a005000, 40K)
+ PRERAM_CBFS_CACHE(0x1a00f000, 68K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.
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