[coreboot-gerrit] New patch to review for coreboot: libpayload: Parse MTC and fill mtc_start and mtc_size
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Tue Jun 16 12:32:14 CEST 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10563
-gerrit
commit 22d6bd91ead0e36c21dd67a13c00478689899ee6
Author: Furquan Shaikh <furquan at google.com>
Date: Wed Jun 10 20:38:48 2015 -0700
libpayload: Parse MTC and fill mtc_start and mtc_size
Parse coreboot table and fill in mtc_start and mtc_size values in
sysinfo structure.
BUG=chrome-os-partner:41125
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: If210ea0a105f6879686e6e930cb29e66bc5e6cd0
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: b70d0d35c85fa1a2317b0239276d5d9e7a550472
Original-Change-Id: I60b6f8ed4c704bd5ad6cce7fce2b9095babe181e
Original-Signed-off-by: Furquan Shaikh <furquan at google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/276778
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang at nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan at chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan at chromium.org>
Original-Tested-by: Furquan Shaikh <furquan at chromium.org>
---
payloads/libpayload/include/coreboot_tables.h | 1 +
payloads/libpayload/include/sysinfo.h | 2 ++
payloads/libpayload/libc/coreboot.c | 11 +++++++++++
3 files changed, 14 insertions(+)
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 649cc2b..eb4c976 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -202,6 +202,7 @@ struct lb_range {
#define CB_TAG_MRC_CACHE 0x0018
#define CB_TAG_ACPI_GNVS 0x0024
#define CB_TAG_WIFI_CALIBRATION 0x0027
+#define CB_TAG_MTC 0x002b
struct cb_cbmem_tab {
uint32_t tag;
uint32_t size;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index bce5c8e..083f19d 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -124,6 +124,8 @@ struct sysinfo_t {
uint32_t sector_size;
uint32_t erase_cmd;
} spi_flash;
+ uint64_t mtc_start;
+ uint32_t mtc_size;
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 999465c..05973cd 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -203,6 +203,14 @@ static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info)
info->ramoops_buffer_size = ramoops->range_size;
}
+static void cb_parse_mtc(void *ptr, struct sysinfo_t *info)
+{
+ struct cb_range *mtc = (struct cb_range *)ptr;
+
+ info->mtc_start = mtc->range_start;
+ info->mtc_size = mtc->range_size;
+}
+
static void cb_parse_spi_flash(void *ptr, struct sysinfo_t *info)
{
struct cb_spi_flash *flash = (struct cb_spi_flash *)ptr;
@@ -361,6 +369,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_SPI_FLASH:
cb_parse_spi_flash(ptr, info);
break;
+ case CB_TAG_MTC:
+ cb_parse_mtc(ptr, info);
+ break;
default:
cb_parse_arch_specific(rec, info);
break;
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