[coreboot-gerrit] New patch to review for coreboot: cpu: port amd/agesa to 64bit
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu Jun 18 10:24:45 CEST 2015
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10579
-gerrit
commit 27787bfb3604b01d4d2bfcd980bf2db415ddb5f4
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Thu Jun 18 01:14:01 2015 -0700
cpu: port amd/agesa to 64bit
Change-Id: I8644b04f4b57db5fc95ec155d3f78d53c63c9831
Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Signed-off-by: Scott Duplichan <scott at notabs.org>
---
src/cpu/amd/agesa/Makefile.inc | 4 +
src/cpu/amd/agesa/cache_as_ram64.inc | 159 +++++++++++++++++++++++++++++++++++
src/cpu/amd/agesa/s3_resume.c | 7 ++
3 files changed, 170 insertions(+)
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 153b2db..485d107 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -27,7 +27,11 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
romstage-y += s3_resume.c
ramstage-y += s3_mtrr.c
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
+else
+cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram64.inc
+endif
romstage-y += heapmanager.c
ramstage-y += heapmanager.c
diff --git a/src/cpu/amd/agesa/cache_as_ram64.inc b/src/cpu/amd/agesa/cache_as_ram64.inc
new file mode 100644
index 0000000..de3a9bc
--- /dev/null
+++ b/src/cpu/amd/agesa/cache_as_ram64.inc
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/******************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * $Workfile:: cache_as_ram.inc
+ *
+ * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
+ *
+ ******************************************************************************
+ */
+
+#include "gcccar.inc"
+#include <cpu/x86/cache.h>
+
+/*
+ * XMM map:
+ * xmm0: BIST
+ * xmm1: backup ebx -- cpu_init_detected
+ */
+
+.code32
+.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
+
+cache_as_ram_setup:
+
+ post_code(0xa0)
+
+ /* enable SSE2 128bit instructions */
+ /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
+
+ movl %cr4, %eax
+ orl $(3<<9), %eax
+ movl %eax, %cr4
+
+ /* Get the cpu_init_detected */
+ mov $1, %eax
+ cpuid
+ shr $24, %ebx
+
+ /* Save the BIST result */
+ cvtsi2sd %ebp, %xmm0
+
+ /* for normal part %ebx already contain cpu_init_detected from fallback call */
+
+ /* Save the cpu_init_detected */
+ cvtsi2sd %ebx, %xmm1
+
+ post_code(0xa1)
+ // AMD_ENABLE_STACK
+
+ post_code(0xa1)
+
+ /* switch to 64 bit long mode */
+ .intel_syntax noprefix
+
+ mov ecx, esi
+ add ecx, 0 # core number
+ xor eax, eax
+ lea edi, [ecx+0x1000+0x23]
+ mov dword ptr [ecx+0], edi
+ mov dword ptr [ecx+4], eax
+
+ lea edi, [ecx+0x1000]
+ mov dword ptr [edi+0x00], 0x000000e3
+ mov dword ptr [edi+0x04], eax
+ mov dword ptr [edi+0x08], 0x400000e3
+ mov dword ptr [edi+0x0c], eax
+ mov dword ptr [edi+0x10], 0x800000e3
+ mov dword ptr [edi+0x14], eax
+ mov dword ptr [edi+0x18], 0xc00000e3
+ mov dword ptr [edi+0x1c], eax
+
+ # load rom based identity mapped page tables
+ mov eax, ecx
+ mov cr3,eax
+
+ # enable PAE
+ mov eax, cr4
+ bts eax, 5
+ mov cr4, eax
+
+ # enable long mode
+ mov ecx, 0xC0000080
+ rdmsr
+ bts eax, 8
+ wrmsr
+
+ # enable paging
+ mov eax, cr0
+ bts eax, 31
+ mov cr0, eax
+
+ # use call far to switch to 64-bit code segment
+ jmp 0x18,.+7
+
+ /* Pass the BIST result */
+ cvtsd2si esi, xmm1
+
+ /* Pass the cpu_init_detected */
+ cvtsd2si edi, xmm0
+
+ /* align the stack */
+ and esp, 0xFFFFFFF0
+
+ .code64
+ call cache_as_ram_main
+ .code32
+
+ .att_syntax prefix
+
+ /* Should never see this postcode */
+ post_code(0xaf)
+stop:
+ jmp stop
+
+disable_cache_as_ram:
+ /* Save return stack */
+ movd 0(%esp), %xmm1
+ movd %esp, %xmm0
+
+ /* Disable cache */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ AMD_DISABLE_STACK
+
+ /* enable cache */
+ movl %cr0, %eax
+ andl $0x9fffffff, %eax
+ movl %eax, %cr0
+ xorl %eax, %eax
+
+ /* Restore the return stack */
+ wbinvd
+ movd %xmm0, %esp
+ movd %xmm1, (%esp)
+ ret
+
+cache_as_ram_setup_out:
+.code64
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 5e07d7a..98671f4 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -56,10 +56,17 @@ static void move_stack_high_mem(void)
memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
/* TODO: We only switch stack on BSP. */
+#ifdef __x86_64__
+ __asm__
+ volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g"
+ (high_stack - BSP_STACK_BASE_ADDR)
+ :);
+#else
__asm__
volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g"
(high_stack - BSP_STACK_BASE_ADDR)
:);
+#endif
}
static void set_resume_cache(void)
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