[coreboot-gerrit] Patch set updated for coreboot: Braswell: Add Braswell SOC support
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Wed Jun 24 21:08:30 CEST 2015
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10051
-gerrit
commit bd96a908012c224f4c4dad2d197227d6ffdc9504
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Mon Apr 20 15:20:28 2015 -0700
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/braswell/Kconfig | 169 ++--
src/soc/intel/braswell/Makefile.inc | 100 +--
src/soc/intel/braswell/acpi.c | 204 +++--
src/soc/intel/braswell/acpi/cpu.asl | 50 +-
src/soc/intel/braswell/acpi/device_nvs.asl | 110 +--
src/soc/intel/braswell/acpi/dptf/cpu.asl | 86 ++-
src/soc/intel/braswell/acpi/dptf/dptf.asl | 11 +-
src/soc/intel/braswell/acpi/dptf/thermal.asl | 12 +-
src/soc/intel/braswell/acpi/dptf/wifi.asl | 16 +
src/soc/intel/braswell/acpi/dptf/wwan.asl | 16 +
src/soc/intel/braswell/acpi/globalnvs.asl | 66 +-
src/soc/intel/braswell/acpi/gpio.asl | 69 +-
src/soc/intel/braswell/acpi/irqlinks.asl | 145 ++--
src/soc/intel/braswell/acpi/irqroute.asl | 6 +-
src/soc/intel/braswell/acpi/lpc.asl | 42 +-
src/soc/intel/braswell/acpi/lpe.asl | 6 +-
src/soc/intel/braswell/acpi/lpss.asl | 24 +-
src/soc/intel/braswell/acpi/pcie.asl | 109 ---
src/soc/intel/braswell/acpi/platform.asl | 18 +-
src/soc/intel/braswell/acpi/scc.asl | 12 +-
src/soc/intel/braswell/acpi/sleepstates.asl | 2 +-
src/soc/intel/braswell/acpi/southcluster.asl | 78 +-
src/soc/intel/braswell/bootblock/Makefile.inc | 2 +-
src/soc/intel/braswell/bootblock/bootblock.c | 9 +-
src/soc/intel/braswell/bootblock/timestamp.inc | 7 +-
src/soc/intel/braswell/chip.c | 280 ++++++-
src/soc/intel/braswell/chip.h | 146 ++--
src/soc/intel/braswell/cpu.c | 116 ++-
src/soc/intel/braswell/dptf.c | 52 --
src/soc/intel/braswell/ehci.c | 181 -----
src/soc/intel/braswell/elog.c | 49 +-
src/soc/intel/braswell/emmc.c | 29 +-
src/soc/intel/braswell/gfx.c | 350 +--------
src/soc/intel/braswell/gpio.c | 423 +++++-----
src/soc/intel/braswell/gpio_support.c | 87 +++
src/soc/intel/braswell/hda.c | 77 +-
src/soc/intel/braswell/include/soc/acpi.h | 17 +-
.../intel/braswell/include/soc/chipset_fsp_util.h | 41 +
src/soc/intel/braswell/include/soc/device_nvs.h | 8 +-
src/soc/intel/braswell/include/soc/efi_wrapper.h | 52 --
src/soc/intel/braswell/include/soc/ehci.h | 24 +-
src/soc/intel/braswell/include/soc/gfx.h | 62 +-
src/soc/intel/braswell/include/soc/gpio.h | 851 ++++++++++++---------
src/soc/intel/braswell/include/soc/hda.h | 45 ++
src/soc/intel/braswell/include/soc/iomap.h | 20 +-
src/soc/intel/braswell/include/soc/iosf.h | 266 ++-----
src/soc/intel/braswell/include/soc/irq.h | 158 ++--
src/soc/intel/braswell/include/soc/lpc.h | 9 +-
src/soc/intel/braswell/include/soc/mrc_wrapper.h | 107 ---
src/soc/intel/braswell/include/soc/msr.h | 19 +-
src/soc/intel/braswell/include/soc/nvs.h | 19 +-
src/soc/intel/braswell/include/soc/pattrs.h | 24 +-
src/soc/intel/braswell/include/soc/pci_devs.h | 87 ++-
src/soc/intel/braswell/include/soc/pcie.h | 10 +-
src/soc/intel/braswell/include/soc/pei_data.h | 62 ++
src/soc/intel/braswell/include/soc/pei_wrapper.h | 30 +
src/soc/intel/braswell/include/soc/pm.h | 267 +++++++
src/soc/intel/braswell/include/soc/pmc.h | 303 --------
src/soc/intel/braswell/include/soc/ramstage.h | 26 +-
src/soc/intel/braswell/include/soc/reset.h | 36 -
src/soc/intel/braswell/include/soc/romstage.h | 38 +-
src/soc/intel/braswell/include/soc/sata.h | 135 +++-
src/soc/intel/braswell/include/soc/smm.h | 22 +-
src/soc/intel/braswell/include/soc/spi.h | 7 +-
src/soc/intel/braswell/include/soc/xhci.h | 15 +-
src/soc/intel/braswell/iosf.c | 261 ++-----
src/soc/intel/braswell/lpe.c | 44 +-
src/soc/intel/braswell/lpss.c | 45 +-
src/soc/intel/braswell/memmap.c | 60 +-
src/soc/intel/braswell/microcode/Makefile.inc | 14 +-
src/soc/intel/braswell/microcode/microcode_blob.c | 21 +-
src/soc/intel/braswell/northcluster.c | 89 ++-
src/soc/intel/braswell/pcie.c | 141 ++--
src/soc/intel/braswell/perf_power.c | 292 -------
src/soc/intel/braswell/placeholders.c | 3 -
src/soc/intel/braswell/pmutil.c | 28 +-
src/soc/intel/braswell/ramstage.c | 88 ++-
src/soc/intel/braswell/refcode.c | 148 ----
src/soc/intel/braswell/reset.c | 47 --
src/soc/intel/braswell/romstage/Makefile.inc | 9 +-
src/soc/intel/braswell/romstage/cache_as_ram.inc | 284 -------
src/soc/intel/braswell/romstage/early_spi.c | 19 +-
src/soc/intel/braswell/romstage/gfx.c | 50 --
src/soc/intel/braswell/romstage/pmc.c | 51 +-
src/soc/intel/braswell/romstage/raminit.c | 185 -----
src/soc/intel/braswell/romstage/romstage.c | 318 +++-----
src/soc/intel/braswell/romstage/uart.c | 38 -
src/soc/intel/braswell/sata.c | 188 +----
src/soc/intel/braswell/scc.c | 82 +-
src/soc/intel/braswell/sd.c | 14 +-
src/soc/intel/braswell/smihandler.c | 227 +++---
src/soc/intel/braswell/smm.c | 24 +-
src/soc/intel/braswell/southcluster.c | 361 ++++-----
src/soc/intel/braswell/spi.c | 129 ++--
src/soc/intel/braswell/spi_loading.c | 154 ++++
src/soc/intel/braswell/stage_cache.c | 35 -
src/soc/intel/braswell/tsc_freq.c | 54 +-
src/soc/intel/braswell/xhci.c | 259 -------
98 files changed, 4005 insertions(+), 5676 deletions(-)
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index d4200c7..dac38ce 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -1,31 +1,45 @@
config SOC_INTEL_BRASWELL
bool
help
- Bay Trail M/D part support.
+ Braswell M/D part support.
if SOC_INTEL_BRASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
select BACKUP_DEFAULT_SMM_REGION
select CACHE_MRC_SETTINGS
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ select CACHE_ROM
+ select CAR_MIGRATION
select COLLECT_TIMESTAMPS
+ select CPU_MICROCODE_IN_CBFS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
- select SUPPORT_CPU_UCODE_IN_CBFS
+ select DYNAMIC_CBMEM
+ select ENABLE_MRC_CACHE
+ select HAS_PRECBMEM_TIMESTAMP_REGION
+ select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
- select RELOCATABLE_RAMSTAGE
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
+ select PLATFORM_USES_FSP1_1
select REG_SCRIPT
+ select SOC_INTEL_COMMON
+ select SOC_INTEL_COMMON_FSP_RAM_INIT
+ select SOC_INTEL_COMMON_FSP_ROMSTAGE
+ select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_STACK
+ select SOC_INTEL_COMMON_STAGE_CACHE
+ select SMM_MODULES
select SMM_TSEG
select SMP
select SPI_FLASH
@@ -35,14 +49,14 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
- select SOC_INTEL_COMMON
+ select USE_GENERIC_FSP_CAR_INC
config BOOTBLOCK_CPU_INIT
string
- default "soc/intel/baytrail/bootblock/bootblock.c"
+ default "soc/intel/braswell/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
- hex
+ hex "PCIe CFG Base Address"
default 0xe0000000
config MAX_CPUS
@@ -61,39 +75,8 @@ config SMM_RESERVED_SIZE
hex
default 0x100000
-config HAVE_MRC
- bool "Add a Memory Reference Code binary"
- default y
- help
- Select this option to add a blob containing
- memory reference code.
- Note: Without this binary coreboot will not work
-
-if HAVE_MRC
-
-config MRC_FILE
- string "Intel memory refeference code path and filename"
- default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin"
- help
- The path and filename of the file to use as System Agent
- binary. Note that this points to the sandybridge binary file
- which is will not work, but it serves its purpose to do builds.
-
-config MRC_BIN_ADDRESS
- hex
- default 0xfffa0000
-
-config MRC_RMT
- bool "Enable MRC RMT training + debug prints"
- default n
-
-endif # HAVE_MRC
-
# Cache As RAM region layout:
#
-# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
-# | MRC usage |
-# | |
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
# | Stack |\
# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
@@ -104,48 +87,63 @@ endif # HAVE_MRC
# | CAR Globals |
# +-------------+ DCACHE_RAM_BASE
#
-# Note that the MRC binary is linked to assume the region marked as "MRC usage"
-# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then
-# a new MRC binary needs to be produced with the updated start and size
-# information.
config DCACHE_RAM_BASE
- hex
- default 0xfe000000
+ hex "Temporary RAM Base Address"
+ default 0xfef00000
config DCACHE_RAM_SIZE
- hex
- default 0x8000
+ hex "Temporary RAM Size"
+ default 0x4000
help
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
-config DCACHE_RAM_MRC_VAR_SIZE
- hex
- default 0x8000
- help
- The amount of cache-as-ram region required by the reference code.
-
config DCACHE_RAM_ROMSTAGE_STACK_SIZE
hex
default 0x800
help
The amount of anticipated stack usage from the data cache
- during pre-RAM ROM stage execution.
+ during pre-ram rom stage execution.
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n
depends on RELOCATABLE_RAMSTAGE
help
- The baytrail romstage code caches the loaded ramstage program
+ The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.
+config CBFS_SIZE
+ hex "Size of CBFS filesystem in ROM"
+ default 0x100000
+ help
+ The firmware image has to store a lot more than just coreboot,
+ including:
+ - a firmware descriptor
+ - Intel Management Engine firmware
+ - MRC cache information
+ This option allows to limit the size of the CBFS portion in the
+ firmware image.
+
+config LOCK_MANAGEMENT_ENGINE
+ bool "Lock Management Engine section"
+ default n
+ help
+ The Intel Management Engine supports preventing write accesses
+ from the host to the Management Engine section in the firmware
+ descriptor. If the ME section is locked, it can only be overwritten
+ with an external SPI flash programmer. You will want this if you
+ want to increase security of your ROM image once you are sure
+ that the ME firmware is no longer going to change.
+
+ If unsure, say N.
+
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
@@ -154,22 +152,6 @@ config ENABLE_BUILTIN_COM1
configure the pads and enable it. This serial port can be used for
the debug console.
-config HAVE_ME_BIN
- bool "Add Intel Management Engine firmware"
- default y
- help
- The Intel processor in the selected system requires a special firmware
- for an integrated controller called Management Engine (ME). The ME
- firmware might be provided in coreboot's 3rdparty repository. If
- not and if you don't have the firmware elsewhere, you can still
- build coreboot without it. In this case however, you'll have to make
- sure that you don't overwrite your ME firmware on your flash ROM.
-
-config ME_BIN_PATH
- string "Path to management engine firmware"
- depends on HAVE_ME_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
-
config HAVE_IFD_BIN
bool
default y
@@ -191,6 +173,26 @@ config BUILD_WITH_FAKE_IFD
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+config HAVE_ME_BIN
+ bool "Add Intel Management Engine firmware"
+ default y
+ help
+ The Intel processor in the selected system requires a special firmware
+ for an integrated controller called Management Engine (ME). The ME
+ firmware might be provided in coreboot's 3rdparty/blobs repository. If
+ not and if you don't have the firmware elsewhere, you can still
+ build coreboot without it. In this case however, you'll have to make
+ sure that you don't overwrite your ME firmware on your flash ROM.
+
+config IED_REGION_SIZE
+ hex
+ default 0x400000
+
+config IFD_BIN_PATH
+ string "Path to intel firmware descriptor"
+ depends on !BUILD_WITH_FAKE_IFD
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+
config IFD_BIOS_SECTION
depends on BUILD_WITH_FAKE_IFD
string
@@ -206,26 +208,9 @@ config IFD_PLATFORM_SECTION
string
default ""
-config IFD_BIN_PATH
- string "Path to intel firmware descriptor"
- depends on !BUILD_WITH_FAKE_IFD
- default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
-
-config HAVE_REFCODE_BLOB
- depends on ARCH_X86
- bool "An external reference code blob should be put into cbfs."
- default n
- help
- The reference code blob will be placed into cbfs.
-
-if HAVE_REFCODE_BLOB
-
-config REFCODE_BLOB_FILE
- string "Path and filename to reference code blob."
- default "refcode.elf"
- help
- The path and filename to the file to be added to cbfs.
-
-endif # HAVE_REFCODE_BLOB
+config ME_BIN_PATH
+ string "Path to management engine firmware"
+ depends on HAVE_ME_BIN
+ default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin"
endif
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 0806bbb..540ac84 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
subdirs-y += bootblock
subdirs-y += microcode
subdirs-y += romstage
+subdirs-y += ../common
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
@@ -10,56 +11,63 @@ subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
-ramstage-y += memmap.c
+romstage-y += gpio_support.c
+romstage-y += iosf.c
romstage-y += memmap.c
-ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
-smm-y += tsc_freq.c
-ramstage-y += spi.c
-smm-y += spi.c
+
+ramstage-y += acpi.c
ramstage-y += chip.c
+ramstage-y += cpu.c
+ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += emmc.c
+ramstage-y += gpio.c
+ifeq ($(CONFIG_GOP_SUPPORT),n)
ramstage-y += gfx.c
+endif
+ramstage-y += hda.c
ramstage-y += iosf.c
-romstage-y += iosf.c
-smm-y += iosf.c
+ramstage-y += lpe.c
+ramstage-y += lpss.c
+ramstage-y += memmap.c
ramstage-y += northcluster.c
-ramstage-y += ramstage.c
-ramstage-y += gpio.c
-romstage-y += reset.c
-ramstage-y += reset.c
-ramstage-y += cpu.c
+ramstage-y += pcie.c
ramstage-y += pmutil.c
-smm-y += pmutil.c
-smm-y += smihandler.c
-ramstage-y += smm.c
-ramstage-y += ehci.c
-ramstage-y += xhci.c
-ramstage-y += southcluster.c
-ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
+ramstage-y += ramstage.c
ramstage-y += sata.c
-ramstage-y += acpi.c
-ramstage-y += lpe.c
ramstage-y += scc.c
-ramstage-y += emmc.c
-ramstage-y += lpss.c
-ramstage-y += pcie.c
ramstage-y += sd.c
-ramstage-y += dptf.c
-ramstage-y += perf_power.c
-ramstage-y += stage_cache.c
-romstage-y += stage_cache.c
-ramstage-$(CONFIG_ELOG) += elog.c
-ramstage-y += hda.c
+ramstage-y += smm.c
+ramstage-y += southcluster.c
+ramstage-y += spi.c
+ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
+ramstage-y += tsc_freq.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
-CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
+smm-y += pmutil.c
+smm-y += smihandler.c
+smm-y += spi.c
+smm-y += tsc_freq.c
+
+CPPFLAGS_common += -I$(src)/arch/x86/include/
+CPPFLAGS_common += -I$(src)/soc/intel/braswell/
+CPPFLAGS_common += -I$(src)/soc/intel/braswell/include
+
+CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
+
+CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include
+CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32
+CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH)
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
-INTERMEDIATE:=baytrail_add_me
+INTERMEDIATE := pch_add_me
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
@@ -70,7 +78,7 @@ else
IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
endif
-baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
+pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
printf "\n** WARNING **\n"
printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
@@ -80,28 +88,30 @@ ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
endif
printf " DD Adding Intel Firmware Descriptor\n"
+ printf "CONFIG_IFD_BIN_PATH: $(CONFIG_IFD_BIN_PATH)\n"
+ printf "IFD_BIN_PATH: $(IFD_BIN_PATH)\n"
dd if=$(IFD_BIN_PATH) \
of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ printf "CONFIG_HAVE_ME_BIN: $(CONFIG_HAVE_ME_BIN)\n"
ifeq ($(CONFIG_HAVE_ME_BIN),y)
printf " IFDTOOL me.bin -> coreboot.pre\n"
+ printf "CONFIG_ME_BIN_PATH: $(CONFIG_ME_BIN_PATH)\n"
$(objutil)/ifdtool/ifdtool \
-i ME:$(CONFIG_ME_BIN_PATH) \
$(obj)/coreboot.pre
mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
endif
-# If an MRC file is an ELF file determine the entry address and first loadable
-# section offset in the file. Subtract the offset from the entry address to
-# determine the final location.
-mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' )
-mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }')
-
-# Add memory reference code blob.
-cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin
-mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE))
-mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS))
-mrc.bin-type := mrc
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+ printf " IFDTOOL Locking Management Engine\n"
+ $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else
+ printf " IFDTOOL Unlocking Management Engine\n"
+ $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+ mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
-PHONY += baytrail_add_me
+PHONY += pch_add_me
endif
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 8357705..e008f07 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,27 +21,30 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
+#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/smp/mpspec.h>
+#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <console/console.h>
-#include <types.h>
-#include <string.h>
-#include <arch/cpu.h>
+#include <cpu/intel/turbo.h>
#include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
#include <cpu/x86/tsc.h>
-#include <cpu/intel/turbo.h>
-
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <ec/google/chromeec/ec.h>
+#include <fsp_gop.h>
#include <soc/acpi.h>
+#include <soc/gfx.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
-#include <soc/pmc.h>
-
-#include <ec/google/chromeec/ec.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <string.h>
+#include <types.h>
#include <vendorcode/google/chromeos/gnvs.h>
#define MWAIT_RES(state, sub_state) \
@@ -89,15 +93,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
-#if CONFIG_CONSOLE_CBMEM
+#if IS_ENABLED(CONFIG_CONSOLE_CBMEM)
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
#endif
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
/* Initialize Verified Boot data */
chromeos_init_vboot(&(gnvs->chromeos));
-#if CONFIG_EC_GOOGLE_CHROMEEC
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
@@ -137,7 +141,7 @@ static int acpi_sci_irq(void)
return sci_irq;
}
-void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+void acpi_create_intel_hpet(acpi_hpet_t *hpet)
{
acpi_header_t *header = &(hpet->header);
acpi_addr_t *addr = &(hpet->addr);
@@ -284,7 +288,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.addrh = 0x0;
}
-static acpi_tstate_t baytrail_tss_table[] = {
+static acpi_tstate_t soc_tss_table[] = {
{ 100, 1000, 0, 0x00, 0 },
{ 88, 875, 0, 0x1e, 0 },
{ 75, 750, 0, 0x1c, 0 },
@@ -295,24 +299,20 @@ static acpi_tstate_t baytrail_tss_table[] = {
{ 13, 125, 0, 0x12, 0 },
};
-static int generate_T_state_entries(int core, int cores_per_package)
+static void generate_T_state_entries(int core, int cores_per_package)
{
- int len;
-
/* Indicate SW_ALL coordination for T-states */
- len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+ acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
/* Indicate FFixedHW so OS will use MSR */
- len += acpigen_write_empty_PTC();
+ acpigen_write_empty_PTC();
/* Set NVS controlled T-state limit */
- len += acpigen_write_TPC("\\TLVL");
+ acpigen_write_TPC("\\TLVL");
/* Write TSS table for MSR access */
- len += acpigen_write_TSS_package(
- ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
-
- return len;
+ acpigen_write_TSS_package(
+ ARRAY_SIZE(soc_tss_table), soc_tss_table);
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
@@ -336,9 +336,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
return (int)power;
}
-static int generate_P_state_entries(int core, int cores_per_package)
+static void generate_P_state_entries(int core, int cores_per_package)
{
- int len, len_pss;
int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock, clock_max;
@@ -366,16 +365,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
- len = acpigen_write_empty_PCT();
+ acpigen_write_empty_PCT();
/* Write _PPC with NVS specified limit on supported P-state */
- len += acpigen_write_PPC_NVS();
+ acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
- len += acpigen_write_PSD_package(core, 1, coord_type);
+ acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
- len += acpigen_write_name("_PSS");
+ acpigen_write_name("_PSS");
/* Determine ratio points */
ratio_step = 1;
@@ -388,36 +387,36 @@ static int generate_P_state_entries(int core, int cores_per_package)
/* P[T] is Turbo state if enabled */
if (get_turbo_state() == TURBO_ENABLED) {
/* _PSS package count including Turbo */
- len_pss = acpigen_write_package(num_entries + 2);
+ acpigen_write_package(num_entries + 2);
ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO];
vid_turbo = pattrs->iacore_vids[IACORE_TURBO];
control_status = (ratio_turbo << 8) | vid_turbo;
/* Add entry for Turbo ratio */
- len_pss += acpigen_write_PSS_package(
- clock_max + 1, /*MHz*/
- power_max, /*mW*/
- 10, /*lat1*/
- 10, /*lat2*/
- control_status, /*control*/
- control_status); /*status*/
+ acpigen_write_PSS_package(
+ clock_max + 1, /* MHz */
+ power_max, /* mW */
+ 10, /* lat1 */
+ 10, /* lat2 */
+ control_status, /* control */
+ control_status); /* status */
} else {
/* _PSS package count without Turbo */
- len_pss = acpigen_write_package(num_entries + 1);
+ acpigen_write_package(num_entries + 1);
ratio_turbo = ratio_max;
vid_turbo = vid_max;
}
/* First regular entry is max non-turbo ratio */
control_status = (ratio_max << 8) | vid_max;
- len_pss += acpigen_write_PSS_package(
- clock_max, /*MHz*/
- power_max, /*mW*/
- 10, /*lat1*/
- 10, /*lat2*/
- control_status, /*control */
- control_status); /*status*/
+ acpigen_write_PSS_package(
+ clock_max, /* MHz */
+ power_max, /* mW */
+ 10, /* lat1 */
+ 10, /* lat2 */
+ control_status, /* control */
+ control_status); /* status */
/* Set up ratio and vid ranges for VID calculation */
ratio_range_2 = (ratio_turbo - ratio_min) * 2;
@@ -439,52 +438,48 @@ static int generate_P_state_entries(int core, int cores_per_package)
clock = (ratio * pattrs->bclk_khz) / 1000;
control_status = (ratio << 8) | (vid & 0xff);
- len_pss += acpigen_write_PSS_package(
- clock, /*MHz*/
- power, /*mW*/
- 10, /*lat1*/
- 10, /*lat2*/
- control_status, /*control*/
- control_status); /*status*/
+ acpigen_write_PSS_package(
+ clock, /* MHz */
+ power, /* mW */
+ 10, /* lat1 */
+ 10, /* lat2 */
+ control_status, /* control */
+ control_status); /* status */
}
/* Fix package length */
- len_pss--;
- acpigen_patch_len(len_pss);
-
- return len + len_pss;
+ acpigen_pop_len();
}
-void generate_cpu_entries(void)
+void generate_cpu_entries(device_t device)
{
- int len_pr, core;
+ int core;
int pcontrol_blk = get_pmbase(), plen = 6;
const struct pattrs *pattrs = pattrs_get();
- for (core=0; core<pattrs->num_cpus; core++) {
+ for (core = 0; core < pattrs->num_cpus; core++) {
if (core > 0) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_PR.CPUx */
- len_pr = acpigen_write_processor(
+ acpigen_write_processor(
core, pcontrol_blk, plen);
/* Generate P-state tables */
- len_pr += generate_P_state_entries(
+ generate_P_state_entries(
core, pattrs->num_cpus);
/* Generate C-state tables */
- len_pr += acpigen_write_CST_package(
+ acpigen_write_CST_package(
cstate_map, ARRAY_SIZE(cstate_map));
/* Generate T-state tables */
- len_pr += generate_T_state_entries(
+ generate_T_state_entries(
core, pattrs->num_cpus);
- len_pr--;
- acpigen_patch_len(len_pr);
+ acpigen_pop_len();
}
}
@@ -505,7 +500,80 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
irqovr = (void *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
- sci_flags);
+ sci_flags);
return current;
}
+
+#if CONFIG_GOP_SUPPORT
+/* Reading VBT table from flash */
+static void get_fsp_vbt(igd_opregion_t *opregion)
+{
+ const optionrom_vbt_t *vbt;
+ uint32_t vbt_len;
+
+ vbt = fsp_get_vbt(&vbt_len);
+ if (!vbt)
+ die("vbt data not found");
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
+ sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
+ sizeof(opregion->vbt.gvd1));
+}
+
+/* Initialize IGD OpRegion, called from ACPI code */
+int init_igd_opregion(igd_opregion_t *opregion)
+{
+ device_t igd;
+ u16 reg16;
+
+ memset(opregion, 0, sizeof(igd_opregion_t));
+
+ /* FIXME if IGD is disabled, we should exit here. */
+
+ memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+ sizeof(IGD_OPREGION_SIGNATURE));
+
+ /* 8kb */
+ opregion->header.size = sizeof(igd_opregion_t) / 1024;
+ opregion->header.version = IGD_OPREGION_VERSION;
+
+ /* FIXME We just assume we're mobile for now */
+ opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+ /* TODO Initialize Mailbox 1 */
+
+ /* TODO Initialize Mailbox 3 */
+ opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
+ opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
+ opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
+ opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
+ opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
+ opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
+ opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
+ opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
+ opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
+ opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
+ opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
+ opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
+ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
+ opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
+ opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
+
+ get_fsp_vbt(opregion);
+
+ /*
+ * TODO This needs to happen in S3 resume, too.
+ * Maybe it should move to the finalize handler
+ */
+ igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC));
+
+ pci_write_config32(igd, ASLS, (u32)opregion);
+ reg16 = pci_read_config16(igd, SWSCI);
+ reg16 &= ~(1 << 0);
+ reg16 |= (1 << 15);
+ pci_write_config16(igd, SWSCI, reg16);
+
+ return 0;
+}
+#endif
diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl
index 85b2014..d487974 100644
--- a/src/soc/intel/braswell/acpi/cpu.asl
+++ b/src/soc/intel/braswell/acpi/cpu.asl
@@ -18,22 +18,34 @@
* Foundation, Inc.
*/
+/* CPU */
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
/* These devices are created at runtime */
-External (\_PR.CP00, DeviceObj)
-External (\_PR.CP01, DeviceObj)
-External (\_PR.CP02, DeviceObj)
-External (\_PR.CP03, DeviceObj)
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+External (\_PR.CPU2, DeviceObj)
+External (\_PR.CPU3, DeviceObj)
+
/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
Method (PNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x81) // _CST
- Notify (\_PR.CP01, 0x81) // _CST
+ Notify (\_PR.CPU0, 0x81) /* _CST */
+ Notify (\_PR.CPU1, 0x81) /* _CST */
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x81) // _CST
- Notify (\_PR.CP03, 0x81) // _CST
+ Notify (\_PR.CPU2, 0x81) /* _CST */
+ Notify (\_PR.CPU3, 0x81) /* _CST */
}
}
@@ -41,12 +53,12 @@ Method (PNOT)
Method (PPCN)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x80) // _PPC
- Notify (\_PR.CP01, 0x80) // _PPC
+ Notify (\_PR.CPU0, 0x80) /* _PPC */
+ Notify (\_PR.CPU1, 0x80) /* _PPC */
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x80) // _PPC
- Notify (\_PR.CP03, 0x80) // _PPC
+ Notify (\_PR.CPU2, 0x80) /* _PPC */
+ Notify (\_PR.CPU3, 0x80) /* _PPC */
}
}
@@ -54,12 +66,12 @@ Method (PPCN)
Method (TNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CP00, 0x82) // _TPC
- Notify (\_PR.CP01, 0x82) // _TPC
+ Notify (\_PR.CPU0, 0x82) /* _TPC */
+ Notify (\_PR.CPU1, 0x82) /* _TPC */
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CP02, 0x82) // _TPC
- Notify (\_PR.CP03, 0x82) // _TPC
+ Notify (\_PR.CPU2, 0x82) /* _TPC */
+ Notify (\_PR.CPU3, 0x82) /* _TPC */
}
}
@@ -67,10 +79,10 @@ Method (TNOT)
Method (PPKG)
{
If (LGreaterEqual (\PCNT, 4)) {
- Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
+ Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3})
} ElseIf (LGreaterEqual (\PCNT, 2)) {
- Return (Package() {\_PR.CP00, \_PR.CP01})
+ Return (Package() {\_PR.CPU0, \_PR.CPU1})
} Else {
- Return (Package() {\_PR.CP00})
+ Return (Package() {\_PR.CPU0})
}
}
diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl
index 1bb7d95..19e4368 100644
--- a/src/soc/intel/braswell/acpi/device_nvs.asl
+++ b/src/soc/intel/braswell/acpi/device_nvs.asl
@@ -20,67 +20,67 @@
/* Device Enabled in ACPI Mode */
-S0EN, 8, // SDMA Enable
-S1EN, 8, // I2C1 Enable
-S2EN, 8, // I2C2 Enable
-S3EN, 8, // I2C3 Enable
-S4EN, 8, // I2C4 Enable
-S5EN, 8, // I2C5 Enable
-S6EN, 8, // I2C6 Enable
-S7EN, 8, // I2C7 Enable
-S8EN, 8, // SDMA2 Enable
-S9EN, 8, // SPI Enable
-SAEN, 8, // PWM1 Enable
-SBEN, 8, // PWM2 Enable
-SCEN, 8, // UART2 Enable
-SDEN, 8, // UART2 Enable
-C0EN, 8, // MMC Enable
-C1EN, 8, // SDIO Enable
-C2EN, 8, // SD Card Enable
-LPEN, 8, // LPE Enable
+S0EN, 8, /* SDMA Enable */
+S1EN, 8, /* I2C1 Enable */
+S2EN, 8, /* I2C2 Enable */
+S3EN, 8, /* I2C3 Enable */
+S4EN, 8, /* I2C4 Enable */
+S5EN, 8, /* I2C5 Enable */
+S6EN, 8, /* I2C6 Enable */
+S7EN, 8, /* I2C7 Enable */
+S8EN, 8, /* SDMA2 Enable */
+S9EN, 8, /* SPI Enable */
+SAEN, 8, /* PWM1 Enable */
+SBEN, 8, /* PWM2 Enable */
+SCEN, 8, /* UART2 Enable */
+SDEN, 8, /* UART2 Enable */
+C0EN, 8, /* MMC Enable */
+C1EN, 8, /* SDIO Enable */
+C2EN, 8, /* SD Card Enable */
+LPEN, 8, /* LPE Enable */
/* BAR 0 */
-S0B0, 32, // SDMA BAR0
-S1B0, 32, // I2C1 BAR0
-S2B0, 32, // I2C2 BAR0
-S3B0, 32, // I2C3 BAR0
-S4B0, 32, // I2C4 BAR0
-S5B0, 32, // I2C5 BAR0
-S6B0, 32, // I2C6 BAR0
-S7B0, 32, // I2C7 BAR0
-S8B0, 32, // SDMA2 BAR0
-S9B0, 32, // SPI BAR0
-SAB0, 32, // PWM1 BAR0
-SBB0, 32, // PWM2 BAR0
-SCB0, 32, // UART1 BAR0
-SDB0, 32, // UART2 BAR0
-C0B0, 32, // MMC BAR0
-C1B0, 32, // SDIO BAR0
-C2B0, 32, // SD Card BAR0
-LPB0, 32, // LPE BAR0
+S0B0, 32, /* SDMA BAR0 */
+S1B0, 32, /* I2C1 BAR0 */
+S2B0, 32, /* I2C2 BAR0 */
+S3B0, 32, /* I2C3 BAR0 */
+S4B0, 32, /* I2C4 BAR0 */
+S5B0, 32, /* I2C5 BAR0 */
+S6B0, 32, /* I2C6 BAR0 */
+S7B0, 32, /* I2C7 BAR0 */
+S8B0, 32, /* SDMA2 BAR0 */
+S9B0, 32, /* SPI BAR0 */
+SAB0, 32, /* PWM1 BAR0 */
+SBB0, 32, /* PWM2 BAR0 */
+SCB0, 32, /* UART1 BAR0 */
+SDB0, 32, /* UART2 BAR0 */
+C0B0, 32, /* MMC BAR0 */
+C1B0, 32, /* SDIO BAR0 */
+C2B0, 32, /* SD Card BAR0 */
+LPB0, 32, /* LPE BAR0 */
/* BAR 1 */
-S0B1, 32, // SDMA BAR1
-S1B1, 32, // I2C1 BAR1
-S2B1, 32, // I2C2 BAR1
-S3B1, 32, // I2C3 BAR1
-S4B1, 32, // I2C4 BAR1
-S5B1, 32, // I2C5 BAR1
-S6B1, 32, // I2C6 BAR1
-S7B1, 32, // I2C7 BAR1
-S8B1, 32, // SDMA2 BAR1
-S9B1, 32, // SPI BAR1
-SAB1, 32, // PWM1 BAR1
-SBB1, 32, // PWM2 BAR1
-SCB1, 32, // UART1 BAR1
-SDB1, 32, // UART2 BAR1
-C0B1, 32, // MMC BAR1
-C1B1, 32, // SDIO BAR1
-C2B1, 32, // SD Card BAR1
-LPB1, 32, // LPE BAR1
+S0B1, 32, /* SDMA BAR1 */
+S1B1, 32, /* I2C1 BAR1 */
+S2B1, 32, /* I2C2 BAR1 */
+S3B1, 32, /* I2C3 BAR1 */
+S4B1, 32, /* I2C4 BAR1 */
+S5B1, 32, /* I2C5 BAR1 */
+S6B1, 32, /* I2C6 BAR1 */
+S7B1, 32, /* I2C7 BAR1 */
+S8B1, 32, /* SDMA2 BAR1 */
+S9B1, 32, /* SPI BAR1 */
+SAB1, 32, /* PWM1 BAR1 */
+SBB1, 32, /* PWM2 BAR1 */
+SCB1, 32, /* UART1 BAR1 */
+SDB1, 32, /* UART2 BAR1 */
+C0B1, 32, /* MMC BAR1 */
+C1B1, 32, /* SDIO BAR1 */
+C2B1, 32, /* SD Card BAR1 */
+LPB1, 32, /* LPE BAR1 */
/* Extra */
-LPFW, 32, // LPE BAR2 Firmware
+LPFW, 32, /* LPE BAR2 Firmware */
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl
index 58c1c7b..9b1930b 100644
--- a/src/soc/intel/braswell/acpi/dptf/cpu.asl
+++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl
@@ -1,13 +1,13 @@
-External (\_PR.CP00._TSS, MethodObj)
-External (\_PR.CP00._TPC, MethodObj)
-External (\_PR.CP00._PTC, PkgObj)
-External (\_PR.CP00._TSD, PkgObj)
-External (\_PR.CP00._PSS, MethodObj)
-
-Device (TCPU)
+External (\_PR.CPU0._TSS, MethodObj)
+External (\_PR.CPU0._TPC, MethodObj)
+External (\_PR.CPU0._PTC, PkgObj)
+External (\_PR.CPU0._TSD, PkgObj)
+External (\_PR.CPU0._PSS, MethodObj)
+External (\_SB.DPTF.CTOK, MethodObj)
+
+Device (B0DB)
{
- Name (_HID, EISAID ("INT3401"))
- Name (_UID, 0)
+ Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */
Method (_STA)
{
@@ -24,8 +24,8 @@ Device (TCPU)
Method (_TSS)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Return (\_PR.CP00._TSS)
+ If (CondRefOf (\_PR.CPU0._TSS)) {
+ Return (\_PR.CPU0._TSS)
} Else {
Return (Package ()
{
@@ -36,8 +36,8 @@ Device (TCPU)
Method (_TPC)
{
- If (CondRefOf (\_PR.CP00._TPC)) {
- Return (\_PR.CP00._TPC)
+ If (CondRefOf (\_PR.CPU0._TPC)) {
+ Return (\_PR.CPU0._TPC)
} Else {
Return (0)
}
@@ -45,8 +45,8 @@ Device (TCPU)
Method (_PTC)
{
- If (CondRefOf (\_PR.CP00._PTC)) {
- Return (\_PR.CP00._PTC)
+ If (CondRefOf (\_PR.CPU0._PTC)) {
+ Return (\_PR.CPU0._PTC)
} Else {
Return (Package ()
{
@@ -58,8 +58,8 @@ Device (TCPU)
Method (_TSD)
{
- If (CondRefOf (\_PR.CP00._TSD)) {
- Return (\_PR.CP00._TSD)
+ If (CondRefOf (\_PR.CPU0._TSD)) {
+ Return (\_PR.CPU0._TSD)
} Else {
Return (Package ()
{
@@ -70,8 +70,8 @@ Device (TCPU)
Method (_TDL)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Store (SizeOf (\_PR.CP00._TSS ()), Local0)
+ If (CondRefOf (\_PR.CPU0._TSS)) {
+ Store (SizeOf (\_PR.CPU0._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -98,8 +98,8 @@ Device (TCPU)
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_PR.CPU0._PSS)) {
+ Return (\_PR.CPU0._PSS)
} Else {
Return (Package ()
{
@@ -113,8 +113,8 @@ Device (TCPU)
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS ()), Local0)
+ } ElseIf (CondRefOf (\_PR.CPU0._PSS)) {
+ Store (SizeOf (\_PR.CPU0._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -127,18 +127,52 @@ Device (TCPU)
{
Return (\_SB.MPPC)
}
-
#ifdef DPTF_CPU_CRITICAL
Method (_CRT)
{
- Return (^^CTOK (DPTF_CPU_CRITICAL))
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL))
}
#endif
#ifdef DPTF_CPU_PASSIVE
Method (_PSV)
{
- Return (^^CTOK (DPTF_CPU_PASSIVE))
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC0
+ Method (_AC0)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC1
+ Method (_AC1)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC2
+ Method (_AC2)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC3
+ Method (_AC3)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))
+ }
+#endif
+
+#ifdef DPTF_CPU_ACTIVE_AC4
+ Method (_AC4)
+ {
+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))
}
#endif
}
diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl
index 9ebfb8c..f8d8347 100644
--- a/src/soc/intel/braswell/acpi/dptf/dptf.asl
+++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl
@@ -1,3 +1,4 @@
+
Device (DPTF)
{
Name (_HID, EISAID ("INT3400"))
@@ -24,7 +25,8 @@ Device (DPTF)
}
}
- /* Arg0: Buffer containing UUID
+ /*
+ * Arg0: Buffer containing UUID
* Arg1: Integer containing Revision ID of buffer format
* Arg2: Integer containing count of entries in Arg3
* Arg3: Buffer containing list of DWORD capabilities
@@ -65,9 +67,6 @@ Device (DPTF)
Return (Local0)
}
- /* Include CPU Participant */
- #include "cpu.asl"
-
/* Include Thermal Participants */
#include "thermal.asl"
@@ -75,4 +74,8 @@ Device (DPTF)
/* Include Charger Participant */
#include "charger.asl"
#endif
+
+ /* Include Network Participants */
+ #include "wifi.asl"
+ #include "wwan.asl"
}
diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl
index 7113215..b123fb6 100644
--- a/src/soc/intel/braswell/acpi/dptf/thermal.asl
+++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl
@@ -60,12 +60,12 @@ Device (TSR0)
Method (_PSV)
{
- Return (^^CTOK (DPTF_TSR0_PASSIVE))
+ Return (CTOK (DPTF_TSR0_PASSIVE))
}
Method (_CRT)
{
- Return (^^CTOK (DPTF_TSR0_CRITICAL))
+ Return (CTOK (DPTF_TSR0_CRITICAL))
}
Name (PATC, 2)
@@ -116,12 +116,12 @@ Device (TSR1)
Method (_PSV)
{
- Return (^^CTOK (DPTF_TSR1_PASSIVE))
+ Return (CTOK (DPTF_TSR1_PASSIVE))
}
Method (_CRT)
{
- Return (^^CTOK (DPTF_TSR1_CRITICAL))
+ Return (CTOK (DPTF_TSR1_CRITICAL))
}
Name (PATC, 2)
@@ -172,12 +172,12 @@ Device (TSR2)
Method (_PSV)
{
- Return (^^CTOK (DPTF_TSR2_PASSIVE))
+ Return (CTOK (DPTF_TSR2_PASSIVE))
}
Method (_CRT)
{
- Return (^^CTOK (DPTF_TSR2_CRITICAL))
+ Return (CTOK (DPTF_TSR2_CRITICAL))
}
Name (PATC, 2)
diff --git a/src/soc/intel/braswell/acpi/dptf/wifi.asl b/src/soc/intel/braswell/acpi/dptf/wifi.asl
new file mode 100644
index 0000000..28da69a
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/wifi.asl
@@ -0,0 +1,16 @@
+Device (WIFI)
+{
+ Name (_HID, "INT3408")
+ Name (_UID, 0)
+ Name (PTYP, 0x07)
+ Name (_STR, Unicode("WIFI wireless device"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+}
diff --git a/src/soc/intel/braswell/acpi/dptf/wwan.asl b/src/soc/intel/braswell/acpi/dptf/wwan.asl
new file mode 100644
index 0000000..f205b8a
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/wwan.asl
@@ -0,0 +1,16 @@
+Device (WWAN)
+{
+ Name (_HID, "INT3408")
+ Name (_UID, 0)
+ Name (PTYP, 0xF)
+ Name (_STR, Unicode("Wireless Wide Area Network"))
+
+ Method (_STA)
+ {
+ If (LEqual (\DPTE, One)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+}
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 36eb98f..fe131f9 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -20,9 +20,10 @@
/* Global Variables */
-Name(\PICM, 0) // IOAPIC/8259
+Name(\PICM, 0) /* IOAPIC/8259 */
-/* Global ACPI memory region. This region is used for passing information
+/*
+ * Global ACPI memory region. This region is used for passing information
* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
* Since we don't know where this will end up in memory at ACPI compile time,
* we have to fix it up in coreboot's ACPI creation phase.
@@ -34,48 +35,49 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
Offset (0x00),
- OSYS, 16, // 0x00 - Operating System
- SMIF, 8, // 0x02 - SMI function
- PRM0, 8, // 0x03 - SMI function parameter
- PRM1, 8, // 0x04 - SMI function parameter
- SCIF, 8, // 0x05 - SCI function
- PRM2, 8, // 0x06 - SCI function parameter
- PRM3, 8, // 0x07 - SCI function parameter
- LCKF, 8, // 0x08 - Global Lock function for EC
- PRM4, 8, // 0x09 - Lock function parameter
- PRM5, 8, // 0x0a - Lock function parameter
- P80D, 32, // 0x0b - Debug port (IO 0x80) value
- LIDS, 8, // 0x0f - LID state (open = 1)
- PWRS, 8, // 0x10 - Power State (AC = 1)
- PCNT, 8, // 0x11 - Processor count
- TPMP, 8, // 0x12 - TPM Present and Enabled
- TLVL, 8, // 0x13 - Throttle Level
- PPCM, 8, // 0x14 - Maximum P-state usable by OS
- PM1I, 32, // 0x15 - System Wake Source - PM1 Index
+ OSYS, 16, /* 0x00 - Operating System */
+ SMIF, 8, /* 0x02 - SMI function */
+ PRM0, 8, /* 0x03 - SMI function parameter */
+ PRM1, 8, /* 0x04 - SMI function parameter */
+ SCIF, 8, /* 0x05 - SCI function */
+ PRM2, 8, /* 0x06 - SCI function parameter */
+ PRM3, 8, /* 0x07 - SCI function parameter */
+ LCKF, 8, /* 0x08 - Global Lock function for EC */
+ PRM4, 8, /* 0x09 - Lock function parameter */
+ PRM5, 8, /* 0x0a - Lock function parameter */
+ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
+ LIDS, 8, /* 0x0f - LID state (open = 1) */
+ PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ PCNT, 8, /* 0x11 - Processor count */
+ TPMP, 8, /* 0x12 - TPM Present and Enabled */
+ TLVL, 8, /* 0x13 - Throttle Level */
+ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */
+ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */
+ BDID, 8, /* 0x19 - Board ID */
/* Device Config */
Offset (0x20),
- S5U0, 8, // 0x20 - Enable USB0 in S5
- S5U1, 8, // 0x21 - Enable USB1 in S5
- S3U0, 8, // 0x22 - Enable USB0 in S3
- S3U1, 8, // 0x23 - Enable USB1 in S3
- TACT, 8, // 0x24 - Thermal Active trip point
- TPSV, 8, // 0x25 - Thermal Passive trip point
- TCRT, 8, // 0x26 - Thermal Critical trip point
- DPTE, 8, // 0x27 - Enable DPTF
+ S5U0, 8, /* 0x20 - Enable USB0 in S5 */
+ S5U1, 8, /* 0x21 - Enable USB1 in S5 */
+ S3U0, 8, /* 0x22 - Enable USB0 in S3 */
+ S3U1, 8, /* 0x23 - Enable USB1 in S3 */
+ TACT, 8, /* 0x24 - Thermal Active trip point */
+ TPSV, 8, /* 0x25 - Thermal Passive trip point */
+ TCRT, 8, /* 0x26 - Thermal Critical trip point */
+ DPTE, 8, /* 0x27 - Enable DPTF */
/* Base addresses */
Offset (0x30),
- CMEM, 32, // 0x30 - CBMEM TOC
- TOLM, 32, // 0x34 - Top of Low Memory
- CBMC, 32, // 0x38 - coreboot mem console pointer
+ CMEM, 32, /* 0x30 - CBMEM TOC */
+ TOLM, 32, /* 0x34 - Top of Low Memory */
+ CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
Offset (0x1000),
- #include <soc/intel/baytrail/acpi/device_nvs.asl>
+ #include <soc/intel/braswell/acpi/device_nvs.asl>
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl
index abe5890..4f1114f 100644
--- a/src/soc/intel/braswell/acpi/gpio.asl
+++ b/src/soc/intel/braswell/acpi/gpio.asl
@@ -21,26 +21,26 @@
#include <soc/iomap.h>
#include <soc/irq.h>
-/* SouthCluster GPIO */
-Device (GPSC)
+/* GPIO SouthWest Community */
+Device (GPSW)
{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
Name (_UID, 1)
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
{
- GPIO_SC_IRQ
+ GPIO_SW_IRQ
}
})
Method (_CRS)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHWEST, RBAS)
Return (^RBUF)
}
@@ -50,26 +50,26 @@ Device (GPSC)
}
}
-/* NorthCluster GPIO */
+/* GPIO North Community */
Device (GPNC)
{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
{
- GPIO_NC_IRQ
+ GPIO_N_IRQ
}
})
Method (_CRS)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPNORTH, RBAS)
Return (^RBUF)
}
@@ -79,26 +79,55 @@ Device (GPNC)
}
}
-/* SUS GPIO */
-Device (GPSS)
+/* GPIO East Community */
+Device (GPEC)
{
- Name (_HID, "INT33FC")
- Name (_CID, "INT33FC")
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
Name (_UID, 3)
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
{
- GPIO_SUS_IRQ
+ GPIO_E_IRQ
}
})
Method (_CRS)
{
CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
- Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPEAST, RBAS)
+ Return (^RBUF)
+ }
+
+ Method (_STA)
+ {
+ Return (0xF)
+ }
+}
+
+/* GPIO SouthEast Community */
+Device (GPSE)
+{
+ Name (_HID, "INT33FF")
+ Name (_CID, "INT33FF")
+ Name (_UID, 4)
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0x8000, RMEM)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+ {
+ GPIO_SE_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+ Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHEAST, RBAS)
Return (^RBUF)
}
diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl
index acc03f0..cb45e13 100644
--- a/src/soc/intel/braswell/acpi/irqlinks.asl
+++ b/src/soc/intel/braswell/acpi/irqlinks.asl
@@ -23,20 +23,20 @@ Device (LNKA)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 1)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTA)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLA, ResourceTemplate()
@@ -45,28 +45,28 @@ Device (LNKA)
})
CreateWordField(RTLA, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTA
+ /* Set the bit from PRTA */
ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
Return (RTLA)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTA)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTA, 0x80)) {
@@ -82,20 +82,20 @@ Device (LNKB)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 2)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTB)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLB, ResourceTemplate()
@@ -104,28 +104,28 @@ Device (LNKB)
})
CreateWordField(RTLB, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTB
+ /* Set the bit from PRTB */
ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
Return (RTLB)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTB)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTB, 0x80)) {
@@ -141,20 +141,20 @@ Device (LNKC)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 3)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTC)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLC, ResourceTemplate()
@@ -163,28 +163,28 @@ Device (LNKC)
})
CreateWordField(RTLC, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTC
+ /* Set the bit from PRTC */
ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
Return (RTLC)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTC)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTC, 0x80)) {
@@ -200,20 +200,20 @@ Device (LNKD)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 4)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTD)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLD, ResourceTemplate()
@@ -222,28 +222,28 @@ Device (LNKD)
})
CreateWordField(RTLD, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTD
+ /* Set the bit from PRTD */
ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
Return (RTLD)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTD)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTD, 0x80)) {
@@ -259,20 +259,20 @@ Device (LNKE)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 5)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTE)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLE, ResourceTemplate()
@@ -281,28 +281,28 @@ Device (LNKE)
})
CreateWordField(RTLE, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTE
+ /* Set the bit from PRTE */
ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
Return (RTLE)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTE)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTE, 0x80)) {
@@ -318,20 +318,20 @@ Device (LNKF)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 6)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTF)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLF, ResourceTemplate()
@@ -340,28 +340,28 @@ Device (LNKF)
})
CreateWordField(RTLF, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTF
+ /* Set the bit from PRTF */
ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
Return (RTLF)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTF)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTF, 0x80)) {
@@ -377,20 +377,20 @@ Device (LNKG)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 7)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTG)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLG, ResourceTemplate()
@@ -399,28 +399,28 @@ Device (LNKG)
})
CreateWordField(RTLG, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTG
+ /* Set the bit from PRTG */
ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
Return (RTLG)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTG)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTG, 0x80)) {
@@ -436,20 +436,20 @@ Device (LNKH)
Name (_HID, EISAID("PNP0C0F"))
Name (_UID, 8)
- // Disable method
+ /* Disable method */
Method (_DIS, 0, Serialized)
{
Store (0x80, PRTH)
}
- // Possible Resource Settings for this Link
+ /* Possible Resource Settings for this Link */
Name (_PRS, ResourceTemplate()
{
IRQ(Level, ActiveLow, Shared)
- { 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+ { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
})
- // Current Resource Settings for this link
+ /* Current Resource Settings for this link */
Method (_CRS, 0, Serialized)
{
Name (RTLH, ResourceTemplate()
@@ -458,28 +458,28 @@ Device (LNKH)
})
CreateWordField(RTLH, 1, IRQ0)
- // Clear the WordField
+ /* Clear the WordField */
Store (Zero, IRQ0)
- // Set the bit from PRTH
+ /* Set the bit from PRTH */
ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
Return (RTLH)
}
- // Set Resource Setting for this IRQ link
+ /* Set Resource Setting for this IRQ link */
Method (_SRS, 1, Serialized)
{
CreateWordField(Arg0, 1, IRQ0)
- // Which bit is set?
+ /* Which bit is set? */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
Store(Local0, PRTH)
}
- // Status
+ /* Status */
Method (_STA, 0, Serialized)
{
If(And(PRTH, 0x80)) {
@@ -489,3 +489,4 @@ Device (LNKH)
}
}
}
+
diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl
index 3a0abe4..32c12ba 100644
--- a/src/soc/intel/braswell/acpi/irqroute.asl
+++ b/src/soc/intel/braswell/acpi/irqroute.asl
@@ -18,19 +18,19 @@
* Foundation, Inc.
*/
-// PCI Interrupt Routing
+/* PCI Interrupt Routing */
Method(_PRT)
{
If (PICM) {
Return (Package() {
#undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
+ #include <soc/intel/braswell/acpi/irq_helper.h>
PCI_DEV_PIRQ_ROUTES
})
} Else {
Return (Package() {
#define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
+ #include <soc/intel/braswell/acpi/irq_helper.h>
PCI_DEV_PIRQ_ROUTES
})
}
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index 8d48ed4..7fa48df 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -19,7 +19,7 @@
* Foundation, Inc.
*/
-// Intel LPC Bus Device - 0:1f.0
+/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
{
@@ -29,7 +29,7 @@ Device (LPCB)
#include "acpi/ec.asl"
- Device (DMAC) // DMA Controller
+ Device (DMAC) /* DMA Controller */
{
Name(_HID, EISAID("PNP0200"))
Name(_CRS, ResourceTemplate()
@@ -42,7 +42,7 @@ Device (LPCB)
})
}
- Device (FWH) // Firmware Hub
+ Device (FWH) /* Firmware Hub */
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
@@ -56,9 +56,9 @@ Device (LPCB)
Name (_HID, EISAID("PNP0103"))
Name (_CID, 0x010CD041)
- Method (_STA, 0) // Device Status
+ Method (_STA, 0) /* Device Status */
{
- Return (0xf) // Enable and show device
+ Return (0xf) /* Enable and show device */
}
Name(_CRS, ResourceTemplate()
@@ -67,7 +67,7 @@ Device (LPCB)
})
}
- Device(PIC) // 8259 Interrupt Controller
+ Device(PIC) /* 8259 Interrupt Controller */
{
Name(_HID,EISAID("PNP0000"))
Name(_CRS, ResourceTemplate()
@@ -93,20 +93,20 @@ Device (LPCB)
})
}
- Device(LDRC) // LPC device: Resource consumption
+ Device(LDRC) /* LPC device: Resource consumption */
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
- IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
- IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
- IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
- IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+ IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+ IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+ IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
})
Method (_CRS, 0, NotSerialized)
@@ -115,18 +115,20 @@ Device (LPCB)
}
}
- Device (RTC) // Real Time Clock
+ Device (RTC) /* Real Time Clock */
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
-// Disable as Windows doesn't like it, and systems don't seem to use it.
-// IRQNoFlags() { 8 }
+/*
+ * Disable as Windows doesn't like it, and systems don't seem to use it.
+ * IRQNoFlags() { 8 }
+ */
})
}
- Device (TIMR) // Intel 8254 timer
+ Device (TIMR) /* Intel 8254 timer */
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
@@ -137,11 +139,11 @@ Device (LPCB)
})
}
- // Include mainboard's superio.asl file.
+ /* Include mainboard's superio.asl file. */
#include "acpi/superio.asl"
#ifdef ENABLE_TPM
- Device (TPM) // Trusted Platform Module
+ Device (TPM) /* Trusted Platform Module */
{
Name(_HID, EISAID("IFX0102"))
Name(_CID, 0x310cd041)
diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl
index 57fa465..001e63d 100644
--- a/src/soc/intel/braswell/acpi/lpe.asl
+++ b/src/soc/intel/braswell/acpi/lpe.asl
@@ -20,10 +20,10 @@
Device (LPEA)
{
- Name (_HID, "80860F28")
- Name (_CID, "80860F28")
+ Name (_HID, "808622A8")
+ Name (_CID, "808622A8")
Name (_UID, 1)
- Name (_DDN, "Low Power Audio Controller")
+ Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8")
Name (_PR0, Package () { PLPE })
Name (RBUF, ResourceTemplate()
diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl
index 2591aa1..ed1ba99 100644
--- a/src/soc/intel/braswell/acpi/lpss.asl
+++ b/src/soc/intel/braswell/acpi/lpss.asl
@@ -84,7 +84,7 @@ Device (SDM2)
Device (I2C1)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 1)
Name (_DDN, "I2C Controller #1")
@@ -143,7 +143,7 @@ Device (I2C1)
Device (I2C2)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 2)
Name (_DDN, "I2C Controller #2")
@@ -202,7 +202,7 @@ Device (I2C2)
Device (I2C3)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 3)
Name (_DDN, "I2C Controller #3")
@@ -261,7 +261,7 @@ Device (I2C3)
Device (I2C4)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 4)
Name (_DDN, "I2C Controller #4")
@@ -320,7 +320,7 @@ Device (I2C4)
Device (I2C5)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 5)
Name (_DDN, "I2C Controller #5")
@@ -379,7 +379,7 @@ Device (I2C5)
Device (I2C6)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 6)
Name (_DDN, "I2C Controller #6")
@@ -438,7 +438,7 @@ Device (I2C6)
Device (I2C7)
{
- Name (_HID, "80860F41")
+ Name (_HID, "808622C1")
Name (_UID, 7)
Name (_DDN, "I2C Controller #7")
@@ -497,7 +497,7 @@ Device (I2C7)
Device (SPI1)
{
- Name (_HID, "80860F0E")
+ Name (_HID, "8086228E")
Name (_UID, 1)
Name (_DDN, "SPI Controller #2")
@@ -550,7 +550,7 @@ Device (SPI1)
Device (PWM1)
{
- Name (_HID, "80860F09")
+ Name (_HID, "80862288")
Name (_UID, 1)
Name (_DDN, "PWM Controller #1")
@@ -578,7 +578,7 @@ Device (PWM1)
Device (PWM2)
{
- Name (_HID, "80860F09")
+ Name (_HID, "80862288")
Name (_UID, 2)
Name (_DDN, "PWM Controller #2")
@@ -606,7 +606,7 @@ Device (PWM2)
Device (UAR1)
{
- Name (_HID, "80860F0A")
+ Name (_HID, "8086228A")
Name (_UID, 1)
Name (_DDN, "HS-UART Controller #1")
@@ -659,7 +659,7 @@ Device (UAR1)
Device (UAR2)
{
- Name (_HID, "80860F0A")
+ Name (_HID, "8086228A")
Name (_UID, 2)
Name (_DDN, "HS-UART Controller #2")
diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl
deleted file mode 100644
index c3f70cc..0000000
--- a/src/soc/intel/braswell/acpi/pcie.asl
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* Intel SOC PCIe support */
-
-Device (RP01)
-{
- Name (_ADR, 0x001c0000)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
- })
- }
- }
-}
-
-Device (RP02)
-{
- Name (_ADR, 0x001c0001)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
- })
- }
- }
-}
-
-Device (RP03)
-{
- Name (_ADR, 0x001c0002)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
- })
- }
- }
-}
-
-Device (RP04)
-{
- Name (_ADR, 0x001c0003)
-
- Method (_PRT)
- {
- If (PICM) {
- Return (Package() {
- #undef PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
- })
- } Else {
- Return (Package() {
- #define PIC_MODE
- #include <soc/intel/baytrail/acpi/irq_helper.h>
- PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
- })
- }
- }
-}
diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl
index 6c27ec3..33be9ee 100644
--- a/src/soc/intel/braswell/acpi/platform.asl
+++ b/src/soc/intel/braswell/acpi/platform.asl
@@ -23,8 +23,8 @@
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
- APMC, 8, // APM command
- APMS, 8 // APM status
+ APMC, 8, /* APM command */
+ APMS, 8 /* APM status */
}
/* Port 80 POST */
@@ -38,12 +38,13 @@ Field (POST, ByteAcc, Lock, Preserve)
/* SMI I/O Trap */
Method(TRAP, 1, Serialized)
{
- Store (Arg0, SMIF) // SMI Function
- Store (0, TRP0) // Generate trap
- Return (SMIF) // Return value of SMI handler
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
}
-/* The _PIC method is called by the OS to choose between interrupt
+/*
+ * The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
@@ -52,11 +53,12 @@ Method(TRAP, 1, Serialized)
Method(_PIC, 1)
{
- // Remember the OS' IRQ routing choice.
+ /* Remember the OS' IRQ routing choice. */
Store(Arg0, PICM)
}
-/* The _PTS method (Prepare To Sleep) is called before the OS is
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl
index 3bf3f39f..3034d25 100644
--- a/src/soc/intel/braswell/acpi/scc.asl
+++ b/src/soc/intel/braswell/acpi/scc.asl
@@ -135,18 +135,18 @@ Device (SDIO)
Device (SDCD)
{
- Name (_HID, "80860F16")
+ Name (_HID, "INT33BB")
Name (_CID, "PNP0D40")
Name (_UID, 3)
Name (_DDN, "SD Card Controller")
Name (RBUF, ResourceTemplate()
{
- Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
- {
- SCC_SD_IRQ
- }
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)
+ Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {SCC_SD_IRQ} /* SD Card IRQ */
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.GPSE", 0, ResourceConsumer, , )
+ {SDCARD_CD} /* SE81 */
})
Method (_CRS)
diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl
index fef196e..8da76b9 100644
--- a/src/soc/intel/braswell/acpi/sleepstates.asl
+++ b/src/soc/intel/braswell/acpi/sleepstates.asl
@@ -19,7 +19,7 @@
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
-// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
Name(\_S3, Package(){0x5,0x5,0x0,0x0})
Name(\_S4, Package(){0x6,0x6,0x0,0x0})
Name(\_S5, Package(){0x7,0x7,0x0,0x0})
+
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index a985f15..25e0bd8 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -23,16 +23,16 @@
Scope(\)
{
- // IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+ /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */
OperationRegion(IO_T, SystemIO, 0x800, 0x10)
Field(IO_T, ByteAcc, NoLock, Preserve)
{
Offset(0x8),
- TRP0, 8 // IO-Trap at 0x808
+ TRP0, 8 /* IO-Trap at 0x808 */
}
- // Intel Legacy Block
+ /* Intel Legacy Block */
OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Field (ILBS, AnyAcc, NoLock, Preserve)
{
@@ -48,8 +48,8 @@ Scope(\)
}
}
-Name(_HID,EISAID("PNP0A08")) // PCIe
-Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_HID,EISAID("PNP0A08")) /* PCIe */
+Name(_CID,EISAID("PNP0A03")) /* PCI */
Name(_ADR, 0)
Name(_BBN, 0)
@@ -58,126 +58,125 @@ Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
- // Bus Numbers
+ /* Bus Numbers */
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
- // IO Region 0
+ /* IO Region 0 */
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
- // PCI Config Space
+ /* PCI Config Space */
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
- // IO Region 1
+ /* IO Region 1 */
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
- // VGA memory (0xa0000-0xbffff)
+ /* VGA memory (0xa0000-0xbffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000,,, ASEG)
- // OPROM reserved (0xc0000-0xc3fff)
+ /* OPROM reserved (0xc0000-0xc3fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000,,, OPR0)
- // OPROM reserved (0xc4000-0xc7fff)
+ /* OPROM reserved (0xc4000-0xc7fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000,,, OPR1)
- // OPROM reserved (0xc8000-0xcbfff)
+ /* OPROM reserved (0xc8000-0xcbfff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000,,, OPR2)
- // OPROM reserved (0xcc000-0xcffff)
+ /* OPROM reserved (0xcc000-0xcffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000,,, OPR3)
- // OPROM reserved (0xd0000-0xd3fff)
+ /* OPROM reserved (0xd0000-0xd3fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000,,, OPR4)
- // OPROM reserved (0xd4000-0xd7fff)
+ /* OPROM reserved (0xd4000-0xd7fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000,,, OPR5)
- // OPROM reserved (0xd8000-0xdbfff)
+ /* OPROM reserved (0xd8000-0xdbfff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000,,, OPR6)
- // OPROM reserved (0xdc000-0xdffff)
+ /* OPROM reserved (0xdc000-0xdffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000,,, OPR7)
- // BIOS Extension (0xe0000-0xe3fff)
+ /* BIOS Extension (0xe0000-0xe3fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000,,, ESG0)
- // BIOS Extension (0xe4000-0xe7fff)
+ /* BIOS Extension (0xe4000-0xe7fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000,,, ESG1)
- // BIOS Extension (0xe8000-0xebfff)
+ /* BIOS Extension (0xe8000-0xebfff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000,,, ESG2)
- // BIOS Extension (0xec000-0xeffff)
+ /* BIOS Extension (0xec000-0xeffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000,,, ESG3)
- // System BIOS (0xf0000-0xfffff)
+ /* System BIOS (0xf0000-0xfffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+ /* PCI Memory Region (Top of memory-0xfeafffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, PMEM)
+ 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
+ 0x00100000,,, PMEM)
- // TPM Area (0xfed40000-0xfed44fff)
+ /* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000,,, TPMR)
})
- // Update PCI resource area
+ /* Update PCI resource area */
CreateDwordField(MCRS, PMEM._MIN, PMIN)
CreateDwordField(MCRS, PMEM._MAX, PMAX)
CreateDwordField(MCRS, PMEM._LEN, PLEN)
- // TOLM is BMBOUND accessible from IOSF so is saved in NVS
+ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
Store (\TOLM, PMIN)
- Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN)
Return (MCRS)
@@ -200,7 +199,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
})
- // Current Resource Settings
+ /* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
Return(PDRS)
@@ -245,29 +244,26 @@ Device (IOSF)
}
}
-// LPC Bridge 0:1f.0
+/* LPC Bridge 0:1f.0 */
#include "lpc.asl"
-// USB XHCI 0:14.0
+/* USB XHCI 0:14.0 */
#include "xhci.asl"
-// IRQ routing for each PCI device
+/* IRQ routing for each PCI device */
#include "irqroute.asl"
-// PCI Express Ports 0:1c.x
-#include "pcie.asl"
-
Scope (\_SB)
{
- // GPIO Devices
+ /* GPIO Devices */
#include "gpio.asl"
- // LPSS Devices
+ /* LPSS Devices */
#include "lpss.asl"
- // SCC Devices
+ /* SCC Devices */
#include "scc.asl"
- // LPE Device
+ /* LPE Device */
#include "lpe.asl"
}
diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
index 3a40251..17d1ee8 100644
--- a/src/soc/intel/braswell/bootblock/Makefile.inc
+++ b/src/soc/intel/braswell/bootblock/Makefile.inc
@@ -1 +1 @@
-chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
+chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 6d31add..f98f694 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -2,13 +2,14 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
@@ -54,10 +55,12 @@ static void setup_mmconfig(void)
{
uint32_t reg;
- /* Set up the MMCONF range. The register lives in the BUNIT. The
+ /*
+ * Set up the MMCONF range. The register lives in the BUNIT. The
* IO variant of the config access needs to be used initially to
* properly configure as the IOSF access registers live in PCI
- * config space. */
+ * config space.
+ */
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
diff --git a/src/soc/intel/braswell/bootblock/timestamp.inc b/src/soc/intel/braswell/bootblock/timestamp.inc
index 3db5c35..e504132 100644
--- a/src/soc/intel/braswell/bootblock/timestamp.inc
+++ b/src/soc/intel/braswell/bootblock/timestamp.inc
@@ -1,6 +1,8 @@
-/* Store the initial timestamp for booting in mmx registers. This works
+/*
+ * Store the initial timestamp for booting in mmx registers. This works
* because the bootblock isn't being compiled with MMX support so mm0 and
- * mm1 will be preserved into romstage. */
+ * mm1 will be preserved into romstage.
+ */
.code32
.global stash_timestamp
@@ -16,3 +18,4 @@ stash_timestamp:
/* Restore the BIST value to %eax */
movl %ebp, %eax
+
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index ecacd5f..c986507 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,17 +18,18 @@
* Foundation, Inc.
*/
+#include <chip.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
-#include <arch/pci_ops.h>
-
+#include <fsp_util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-#include "chip.h"
static void pci_domain_set_resources(device_t dev)
{
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
assign_resources(dev->link_list);
}
@@ -40,17 +42,35 @@ static struct device_operations pci_domain_ops = {
.ops_pci_bus = pci_bus_default_ops,
};
+static void cpu_bus_noop(device_t dev) { }
+
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = baytrail_init_cpus,
- .scan_bus = NULL,
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = soc_init_cpus
};
static void enable_dev(device_t dev)
{
+ printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n",
+ __FILE__, __func__,
+ dev_name(dev), dev->path.type);
+ printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",
+ pci_read_config16(dev, PCI_VENDOR_ID),
+ pci_read_config16(dev, PCI_DEVICE_ID));
+ printk(BIOS_SPEW, "class: 0x%02x %s\n"
+ "subclass: 0x%02x %s\n"
+ "prog: 0x%02x\n"
+ "revision: 0x%02x\n",
+ pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8,
+ get_pci_class_name(dev),
+ pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff,
+ get_pci_subclass_name(dev),
+ pci_read_config8(dev, PCI_CLASS_PROG),
+ pci_read_config8(dev, PCI_REVISION_ID));
+
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
@@ -65,20 +85,258 @@ static void enable_dev(device_t dev)
}
}
+void soc_silicon_init_params(SILICON_INIT_UPD *params)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ struct soc_intel_braswell_config *config = dev->chip_info;
+
+ /* Set the parameters for SiliconInit */
+ printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
+ params->PcdSdcardMode = config->PcdSdcardMode;
+ params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
+ params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
+ params->PcdEnableAzalia = config->PcdEnableAzalia;
+ params->AzaliaConfigPtr = config->AzaliaConfigPtr;
+ params->PcdEnableSata = config->PcdEnableSata;
+ params->PcdEnableXhci = config->PcdEnableXhci;
+ params->PcdEnableLpe = config->PcdEnableLpe;
+ params->PcdEnableDma0 = config->PcdEnableDma0;
+ params->PcdEnableDma1 = config->PcdEnableDma1;
+ params->PcdEnableI2C0 = config->PcdEnableI2C0;
+ params->PcdEnableI2C1 = config->PcdEnableI2C1;
+ params->PcdEnableI2C2 = config->PcdEnableI2C2;
+ params->PcdEnableI2C3 = config->PcdEnableI2C3;
+ params->PcdEnableI2C4 = config->PcdEnableI2C4;
+ params->PcdEnableI2C5 = config->PcdEnableI2C5;
+ params->PcdEnableI2C6 = config->PcdEnableI2C6;
+ params->PcdGraphicsConfigPtr = config->PcdGraphicsConfigPtr;
+ params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
+ params->ChvSvidConfig = config->ChvSvidConfig;
+ params->DptfDisable = config->DptfDisable;
+ params->PcdEmmcMode = config->PcdEmmcMode;
+ params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc;
+ params->PcdDispClkSsc = config->PcdDispClkSsc;
+ params->PcdSataClkSsc = config->PcdSataClkSsc;
+ params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet;
+ params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
+ params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn;
+ params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf;
+ params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet;
+ params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet;
+ params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn;
+ params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf;
+ params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet;
+ params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet;
+ params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn;
+ params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf;
+ params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet;
+ params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet;
+ params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn;
+ params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf;
+ params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet;
+ params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet;
+ params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn;
+ params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf;
+ params->Usb3Lane0Ow2tapgen2deemph3p5 =
+ config->Usb3Lane0Ow2tapgen2deemph3p5;
+ params->Usb3Lane1Ow2tapgen2deemph3p5 =
+ config->Usb3Lane1Ow2tapgen2deemph3p5;
+ params->Usb3Lane2Ow2tapgen2deemph3p5 =
+ config->Usb3Lane2Ow2tapgen2deemph3p5;
+ params->Usb3Lane3Ow2tapgen2deemph3p5 =
+ config->Usb3Lane3Ow2tapgen2deemph3p5;
+ params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed;
+ params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort;
+ params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort;
+ params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed;
+ params->PcdPchSsicEnable = config->PcdPchSsicEnable;
+ params->PcdLogoPtr = config->PcdLogoPtr;
+ params->PcdLogoSize = config->PcdLogoSize;
+ params->PcdRtcLock = config->PcdRtcLock;
+ params->PMIC_I2CBus = config->PMIC_I2CBus;
+ params->ISPEnable = config->ISPEnable;
+ params->ISPPciDevConfig = config->ISPPciDevConfig;
+}
+
+void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
+ SILICON_INIT_UPD *new)
+{
+ /* Display the parameters for SiliconInit */
+ printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
+ soc_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode,
+ new->PcdSdcardMode);
+ soc_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0,
+ new->PcdEnableHsuart0);
+ soc_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1,
+ new->PcdEnableHsuart1);
+ soc_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia,
+ new->PcdEnableAzalia);
+ soc_display_upd_value("AzaliaVerbTablePtr", 4,
+ (uint32_t)old->AzaliaVerbTablePtr,
+ (uint32_t)new->AzaliaVerbTablePtr);
+ soc_display_upd_value("AzaliaConfigPtr", 4, old->AzaliaConfigPtr,
+ new->AzaliaConfigPtr);
+ soc_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata,
+ new->PcdEnableSata);
+ soc_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci,
+ new->PcdEnableXhci);
+ soc_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe,
+ new->PcdEnableLpe);
+ soc_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0,
+ new->PcdEnableDma0);
+ soc_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1,
+ new->PcdEnableDma1);
+ soc_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0,
+ new->PcdEnableI2C0);
+ soc_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1,
+ new->PcdEnableI2C1);
+ soc_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2,
+ new->PcdEnableI2C2);
+ soc_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3,
+ new->PcdEnableI2C3);
+ soc_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4,
+ new->PcdEnableI2C4);
+ soc_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5,
+ new->PcdEnableI2C5);
+ soc_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6,
+ new->PcdEnableI2C6);
+ soc_display_upd_value("PcdGraphicsConfigPtr", 4,
+ old->PcdGraphicsConfigPtr, new->PcdGraphicsConfigPtr);
+ soc_display_upd_value("GpioFamilyInitTablePtr", 4,
+ (uint32_t)old->GpioFamilyInitTablePtr,
+ (uint32_t)new->GpioFamilyInitTablePtr);
+ soc_display_upd_value("GpioPadInitTablePtr", 4,
+ (uint32_t)old->GpioPadInitTablePtr,
+ (uint32_t)new->GpioPadInitTablePtr);
+ soc_display_upd_value("PunitPwrConfigDisable", 1,
+ old->PunitPwrConfigDisable,
+ new->PunitPwrConfigDisable);
+ soc_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig,
+ new->ChvSvidConfig);
+ soc_display_upd_value("DptfDisable", 1, old->DptfDisable,
+ new->DptfDisable);
+ soc_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode,
+ new->PcdEmmcMode);
+ soc_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc,
+ new->PcdUsb3ClkSsc);
+ soc_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc,
+ new->PcdDispClkSsc);
+ soc_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc,
+ new->PcdSataClkSsc);
+ soc_display_upd_value("Usb2Port0PerPortPeTxiSet", 1,
+ old->Usb2Port0PerPortPeTxiSet,
+ new->Usb2Port0PerPortPeTxiSet);
+ soc_display_upd_value("Usb2Port0PerPortTxiSet", 1,
+ old->Usb2Port0PerPortTxiSet,
+ new->Usb2Port0PerPortTxiSet);
+ soc_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1,
+ old->Usb2Port0IUsbTxEmphasisEn,
+ new->Usb2Port0IUsbTxEmphasisEn);
+ soc_display_upd_value("Usb2Port0PerPortTxPeHalf", 1,
+ old->Usb2Port0PerPortTxPeHalf,
+ new->Usb2Port0PerPortTxPeHalf);
+ soc_display_upd_value("Usb2Port1PerPortPeTxiSet", 1,
+ old->Usb2Port1PerPortPeTxiSet,
+ new->Usb2Port1PerPortPeTxiSet);
+ soc_display_upd_value("Usb2Port1PerPortTxiSet", 1,
+ old->Usb2Port1PerPortTxiSet,
+ new->Usb2Port1PerPortTxiSet);
+ soc_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1,
+ old->Usb2Port1IUsbTxEmphasisEn,
+ new->Usb2Port1IUsbTxEmphasisEn);
+ soc_display_upd_value("Usb2Port1PerPortTxPeHalf", 1,
+ old->Usb2Port1PerPortTxPeHalf,
+ new->Usb2Port1PerPortTxPeHalf);
+ soc_display_upd_value("Usb2Port2PerPortPeTxiSet", 1,
+ old->Usb2Port2PerPortPeTxiSet,
+ new->Usb2Port2PerPortPeTxiSet);
+ soc_display_upd_value("Usb2Port2PerPortTxiSet", 1,
+ old->Usb2Port2PerPortTxiSet,
+ new->Usb2Port2PerPortTxiSet);
+ soc_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1,
+ old->Usb2Port2IUsbTxEmphasisEn,
+ new->Usb2Port2IUsbTxEmphasisEn);
+ soc_display_upd_value("Usb2Port2PerPortTxPeHalf", 1,
+ old->Usb2Port2PerPortTxPeHalf,
+ new->Usb2Port2PerPortTxPeHalf);
+ soc_display_upd_value("Usb2Port3PerPortPeTxiSet", 1,
+ old->Usb2Port3PerPortPeTxiSet,
+ new->Usb2Port3PerPortPeTxiSet);
+ soc_display_upd_value("Usb2Port3PerPortTxiSet", 1,
+ old->Usb2Port3PerPortTxiSet,
+ new->Usb2Port3PerPortTxiSet);
+ soc_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1,
+ old->Usb2Port3IUsbTxEmphasisEn,
+ new->Usb2Port3IUsbTxEmphasisEn);
+ soc_display_upd_value("Usb2Port3PerPortTxPeHalf", 1,
+ old->Usb2Port3PerPortTxPeHalf,
+ new->Usb2Port3PerPortTxPeHalf);
+ soc_display_upd_value("Usb2Port4PerPortPeTxiSet", 1,
+ old->Usb2Port4PerPortPeTxiSet,
+ new->Usb2Port4PerPortPeTxiSet);
+ soc_display_upd_value("Usb2Port4PerPortTxiSet", 1,
+ old->Usb2Port4PerPortTxiSet,
+ new->Usb2Port4PerPortTxiSet);
+ soc_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1,
+ old->Usb2Port4IUsbTxEmphasisEn,
+ new->Usb2Port4IUsbTxEmphasisEn);
+ soc_display_upd_value("Usb2Port4PerPortTxPeHalf", 1,
+ old->Usb2Port4PerPortTxPeHalf,
+ new->Usb2Port4PerPortTxPeHalf);
+ soc_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1,
+ old->Usb3Lane0Ow2tapgen2deemph3p5,
+ new->Usb3Lane0Ow2tapgen2deemph3p5);
+ soc_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1,
+ old->Usb3Lane1Ow2tapgen2deemph3p5,
+ new->Usb3Lane1Ow2tapgen2deemph3p5);
+ soc_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1,
+ old->Usb3Lane2Ow2tapgen2deemph3p5,
+ new->Usb3Lane2Ow2tapgen2deemph3p5);
+ soc_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1,
+ old->Usb3Lane3Ow2tapgen2deemph3p5,
+ new->Usb3Lane3Ow2tapgen2deemph3p5);
+ soc_display_upd_value("PcdSataInterfaceSpeed", 1,
+ old->PcdSataInterfaceSpeed,
+ new->PcdSataInterfaceSpeed);
+ soc_display_upd_value("PcdPchUsbSsicPort", 1,
+ old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort);
+ soc_display_upd_value("PcdPchUsbHsicPort", 1,
+ old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort);
+ soc_display_upd_value("PcdPcieRootPortSpeed", 1,
+ old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed);
+ soc_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable,
+ new->PcdPchSsicEnable);
+ soc_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr,
+ new->PcdLogoPtr);
+ soc_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize,
+ new->PcdLogoSize);
+ soc_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock,
+ new->PcdRtcLock);
+ soc_display_upd_value("PMIC_I2CBus", 1,
+ old->PMIC_I2CBus, new->PMIC_I2CBus);
+ soc_display_upd_value("ISPEnable", 1,
+ old->ISPEnable, new->ISPEnable);
+ soc_display_upd_value("ISPPciDevConfig", 1,
+ old->ISPPciDevConfig, new->ISPPciDevConfig);
+}
+
/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
static void soc_init(void *chip_info)
{
- baytrail_init_pre_device(chip_info);
+ printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);
+ soc_init_pre_device(chip_info);
}
-struct chip_operations soc_intel_baytrail_ops = {
- CHIP_NAME("Intel BayTrail SoC")
+struct chip_operations soc_intel_braswell_ops = {
+ CHIP_NAME("Intel Braswell SoC")
.enable_dev = enable_dev,
.init = soc_init,
};
static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
+ printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n",
+ __FILE__, __func__, dev_name(dev), vendor, device);
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_read_config32(dev, PCI_VENDOR_ID));
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index ffcf54c..fde508c 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,46 +18,28 @@
* Foundation, Inc.
*/
-/* The devicetree parser expects chip.h to reside directly in the path
- * specified by the devicetree. */
+/*
+ * The devicetree parser expects chip.h to reside directly in the path
+ * specified by the devicetree.
+ */
-#ifndef _BAYTRAIL_CHIP_H_
-#define _BAYTRAIL_CHIP_H_
+#ifndef _SOC_CHIP_H_
+#define _SOC_CHIP_H_
#include <stdint.h>
+#include <fsp_util.h>
+#include <soc/pci_devs.h>
+
+#define SVID_CONFIG1 1
+#define SVID_CONFIG3 3
-struct soc_intel_baytrail_config {
+struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
- uint8_t sata_port_map;
- uint8_t sata_ahci;
- uint8_t ide_legacy_combined;
uint8_t clkreq_enable;
- /* VR low power settings -- enable PS2 mode for gfx and core */
- int vnn_ps2_enable;
- int vcc_ps2_enable;
-
/* Disable SLP_X stretching after SUS power well loss. */
int disable_slp_x_stretch_sus_fail;
- /* USB Port Disable mask */
- uint16_t usb2_port_disable_mask;
- uint16_t usb3_port_disable_mask;
-
- /* USB routing */
- int usb_route_to_xhci;
-
- /* USB PHY settings specific to the board */
- uint32_t usb2_per_port_lane0;
- uint32_t usb2_per_port_rcomp_hs_pullup0;
- uint32_t usb2_per_port_lane1;
- uint32_t usb2_per_port_rcomp_hs_pullup1;
- uint32_t usb2_per_port_lane2;
- uint32_t usb2_per_port_rcomp_hs_pullup2;
- uint32_t usb2_per_port_lane3;
- uint32_t usb2_per_port_rcomp_hs_pullup3;
- uint32_t usb2_comp_bg;
-
/* LPE Audio Clock configuration. */
int lpe_codec_clk_freq; /* 19 or 25 are valid. */
int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
@@ -67,29 +50,94 @@ struct soc_intel_baytrail_config {
/* Enable devices in ACPI mode */
int lpss_acpi_mode;
- int scc_acpi_mode;
+ int emmc_acpi_mode;
+ int sd_acpi_mode;
int lpe_acpi_mode;
/* Allow PCIe devices to wake system from suspend. */
int pcie_wake_enable;
- int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */
- uint16_t gpu_pipea_power_on_delay;
- uint16_t gpu_pipea_light_on_delay;
- uint16_t gpu_pipea_power_off_delay;
- uint16_t gpu_pipea_light_off_delay;
- uint16_t gpu_pipea_power_cycle_delay;
- int gpu_pipea_pwm_freq_hz;
-
- int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
- uint16_t gpu_pipeb_power_on_delay;
- uint16_t gpu_pipeb_light_on_delay;
- uint16_t gpu_pipeb_power_off_delay;
- uint16_t gpu_pipeb_light_off_delay;
- uint16_t gpu_pipeb_power_cycle_delay;
- int gpu_pipeb_pwm_freq_hz;
- int disable_ddr_2x_refresh_rate;
+ /*
+ * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
+ * These are configuration values that are passed to FSP during
+ * MemoryInit.
+ */
+ UINT16 PcdMrcInitTsegSize;
+ UINT16 PcdMrcInitMmioSize;
+ UINT8 PcdMrcInitSpdAddr1;
+ UINT8 PcdMrcInitSpdAddr2;
+ UINT8 PcdIgdDvmt50PreAlloc;
+ UINT8 PcdApertureSize;
+ UINT8 PcdGttSize;
+ UINT8 PcdLegacySegDecode;
+
+ /*
+ * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
+ * These are configuration values that are passed to FSP during
+ * SiliconInit.
+ */
+ UINT8 PcdSdcardMode;
+ UINT8 PcdEnableHsuart0;
+ UINT8 PcdEnableHsuart1;
+ UINT8 PcdEnableAzalia;
+ UINT32 AzaliaConfigPtr;
+ UINT8 PcdEnableSata;
+ UINT8 PcdEnableXhci;
+ UINT8 PcdEnableLpe;
+ UINT8 PcdEnableDma0;
+ UINT8 PcdEnableDma1;
+ UINT8 PcdEnableI2C0;
+ UINT8 PcdEnableI2C1;
+ UINT8 PcdEnableI2C2;
+ UINT8 PcdEnableI2C3;
+ UINT8 PcdEnableI2C4;
+ UINT8 PcdEnableI2C5;
+ UINT8 PcdEnableI2C6;
+ UINT32 PcdGraphicsConfigPtr;
+ UINT8 PunitPwrConfigDisable;
+ UINT8 ChvSvidConfig;
+ UINT8 DptfDisable;
+ UINT8 PcdEmmcMode;
+ UINT8 PcdUsb3ClkSsc;
+ UINT8 PcdDispClkSsc;
+ UINT8 PcdSataClkSsc;
+ UINT8 Usb2Port0PerPortPeTxiSet;
+ UINT8 Usb2Port0PerPortTxiSet;
+ UINT8 Usb2Port0IUsbTxEmphasisEn;
+ UINT8 Usb2Port0PerPortTxPeHalf;
+ UINT8 Usb2Port1PerPortPeTxiSet;
+ UINT8 Usb2Port1PerPortTxiSet;
+ UINT8 Usb2Port1IUsbTxEmphasisEn;
+ UINT8 Usb2Port1PerPortTxPeHalf;
+ UINT8 Usb2Port2PerPortPeTxiSet;
+ UINT8 Usb2Port2PerPortTxiSet;
+ UINT8 Usb2Port2IUsbTxEmphasisEn;
+ UINT8 Usb2Port2PerPortTxPeHalf;
+ UINT8 Usb2Port3PerPortPeTxiSet;
+ UINT8 Usb2Port3PerPortTxiSet;
+ UINT8 Usb2Port3IUsbTxEmphasisEn;
+ UINT8 Usb2Port3PerPortTxPeHalf;
+ UINT8 Usb2Port4PerPortPeTxiSet;
+ UINT8 Usb2Port4PerPortTxiSet;
+ UINT8 Usb2Port4IUsbTxEmphasisEn;
+ UINT8 Usb2Port4PerPortTxPeHalf;
+ UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
+ UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
+ UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
+ UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
+ UINT8 PcdSataInterfaceSpeed;
+ UINT8 PcdPchUsbSsicPort;
+ UINT8 PcdPchUsbHsicPort;
+ UINT8 PcdPcieRootPortSpeed;
+ UINT8 PcdPchSsicEnable;
+ UINT32 PcdLogoPtr;
+ UINT32 PcdLogoSize;
+ UINT8 PcdRtcLock;
+ UINT8 PMIC_I2CBus;
+ UINT8 ISPEnable;
+ UINT8 ISPPciDevConfig;
};
-extern struct chip_operations soc_intel_baytrail_ops;
-#endif /* _BAYTRAIL_CHIP_H_ */
+extern struct chip_operations soc_intel_braswell_ops;
+
+#endif /* _SOC_CHIP_H_ */
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 6b84c59..3abec6b 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,7 +18,6 @@
* Foundation, Inc.
*/
-#include <stdlib.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/microcode.h>
@@ -28,64 +28,42 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
-#include <reg_script.h>
-
-#include <soc/iosf.h>
+#include <soc/intel/common/memmap.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/ramstage.h>
#include <soc/smm.h>
+#include <stdlib.h>
static void smm_relocate(void *unused);
static void enable_smis(void *unused);
+static void pre_smm_relocation(void *unused);
static struct mp_flight_record mp_steps[] = {
+ MP_FR_BLOCK_APS(pre_smm_relocation, NULL, pre_smm_relocation, NULL),
MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL),
MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL),
/* Wait for APs to finish initialization before proceeding. */
MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
};
-/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
+/* The APIC id space is sparse. Each id is separated by 2. */
static int adjust_apic_id(int index, int apic_id)
{
return 2 * index;
}
-/* Package level MSRs */
-const struct reg_script package_msr_script[] = {
- /* Set Package TDP to ~7W */
- REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa),
- REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0),
- REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702),
- REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b),
- REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0),
- REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305),
- REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d),
- REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27),
- REG_SCRIPT_END
-};
-/* Core level MSRs */
-const struct reg_script core_msr_script[] = {
- /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
- REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
- REG_MSR_RMW(MSR_POWER_MISC,
- ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
- /* Disable C1E */
- REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
- REG_MSR_OR(MSR_POWER_MISC, 0x44),
- REG_SCRIPT_END
-};
-
-void baytrail_init_cpus(device_t dev)
+void soc_init_cpus(device_t dev)
{
struct bus *cpu_bus = dev->link_list;
const struct pattrs *pattrs = pattrs_get();
struct mp_params mp_params;
- uint32_t bsmrwac;
void *default_smm_area;
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
+
/* Set up MTRRs based on physical address size. */
x86_setup_fixed_mtrrs();
x86_setup_var_mtrrs(pattrs->address_bits, 2);
@@ -100,52 +78,22 @@ void baytrail_init_cpus(device_t dev)
default_smm_area = backup_default_smm_area();
- /*
- * Configure the BUNIT to allow dirty cache line evictions in non-SMM
- * mode for the lines that were dirtied while in SMM mode. Otherwise
- * the writes would be silently dropped.
- */
- bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
- iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
-
- /* Set package MSRs */
- reg_script_run(package_msr_script);
-
- /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */
enable_turbo();
- if (mp_init(cpu_bus, &mp_params)) {
+ if (mp_init(cpu_bus, &mp_params))
printk(BIOS_ERR, "MP initialization failure.\n");
- }
restore_default_smm_area(default_smm_area);
}
-static void baytrail_core_init(device_t cpu)
-{
- printk(BIOS_DEBUG, "Init BayTrail core.\n");
-
- /* On bay trail the turbo disable bit is actually scoped at building
- * block level -- not package. For non-bsp cores that are within a
- * building block enable turbo. The cores within the BSP's building
- * block will just see it already enabled and move on. */
- if (lapicid())
- enable_turbo();
-
- /* Set core MSRs */
- reg_script_run(core_msr_script);
-
- /* Set this core to max frequency ratio */
- set_max_freq();
-}
static struct device_operations cpu_dev_ops = {
- .init = baytrail_core_init,
+ .init = NULL,
};
static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_INTEL, 0x30673 },
- { X86_VENDOR_INTEL, 0x30678 },
+ { X86_VENDOR_INTEL, 0x406C3 },
+ { X86_VENDOR_INTEL, 0x406C2 },
{ 0, 0 },
};
@@ -202,9 +150,11 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
smrr.hi = 0;
wrmsr(SMRRphysMask_MSR, smrr);
- /* The relocated handler runs with all CPUs concurrently. Therefore
+ /*
+ * The relocated handler runs with all CPUs concurrently. Therefore
* stagger the entry points adjusting SMBASE downwards by save state
- * size * CPU num. */
+ * size * CPU num.
+ */
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase);
smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size;
printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase);
@@ -232,8 +182,10 @@ static int install_relocation_handler(int num_cpus)
static int install_permanent_handler(int num_cpus)
{
- /* There are num_cpus concurrent stacks and num_cpus concurrent save
- * state areas. Lastly, set the stack size to the save state size. */
+ /*
+ * There are num_cpus concurrent stacks and num_cpus concurrent save
+ * state areas. Lastly, set the stack size to the save state size.
+ */
int save_state_size = sizeof(em64t100_smm_state_save_area_t);
struct smm_loader_params smm_params = {
.per_cpu_stack_size = save_state_size,
@@ -241,11 +193,15 @@ static int install_permanent_handler(int num_cpus)
.per_cpu_save_state_size = save_state_size,
.num_concurrent_save_states = num_cpus,
};
- const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE;
+ void *smm_base;
+ size_t smm_size;
+ int tseg_size;
printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
relo_attrs.smbase);
+ smm_region(&smm_base, &smm_size);
+ tseg_size = smm_size - CONFIG_SMM_RESERVED_SIZE;
if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params))
return -1;
@@ -259,11 +215,14 @@ static int smm_load_handlers(void)
/* All range registers are aligned to 4KiB */
const uint32_t rmask = ~((1 << 12) - 1);
const struct pattrs *pattrs = pattrs_get();
+ void *smm_base;
+ size_t smm_size;
/* Initialize global tracking state. */
- relo_attrs.smbase = (uint32_t)smm_region_start();
+ smm_region(&smm_base, &smm_size);
+ relo_attrs.smbase = (uint32_t)smm_base;
relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
- relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask;
+ relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
relo_attrs.smrr_mask |= MTRRphysMaskValid;
/* Install handlers. */
@@ -283,6 +242,17 @@ static int smm_load_handlers(void)
return 0;
}
+static void pre_smm_relocation(void *unused)
+{
+ const struct pattrs *pattrs = pattrs_get();
+ msr_t msr_value;
+
+ /* Need to make sure that all cores have microcode loaded. */
+ msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID);
+ if (msr_value.hi == 0)
+ intel_microcode_load_unlocked(pattrs->microcode_patch);
+}
+
static void smm_relocate(void *unused)
{
const struct pattrs *pattrs = pattrs_get();
diff --git a/src/soc/intel/braswell/dptf.c b/src/soc/intel/braswell/dptf.c
deleted file mode 100644
index 79a000d..0000000
--- a/src/soc/intel/braswell/dptf.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <bootstate.h>
-#include <console/console.h>
-#include <reg_script.h>
-#include <soc/iosf.h>
-
-static const struct reg_script dptf_init_settings[] = {
- /* SocThermInit */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029),
- /* ratio 11 = 1466mhz for mid and entry celeron */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002),
- REG_SCRIPT_END,
-};
-
-static void dptf_init(void *unused)
-{
- printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n");
- reg_script_run(dptf_init_settings);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL);
diff --git a/src/soc/intel/braswell/ehci.c b/src/soc/intel/braswell/ehci.c
deleted file mode 100644
index fce1ba7..0000000
--- a/src/soc/intel/braswell/ehci.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-#include <arch/acpi.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <stdint.h>
-#include <reg_script.h>
-
-#include <soc/iomap.h>
-#include <soc/iosf.h>
-#include <soc/pci_devs.h>
-#include <soc/pmc.h>
-#include <soc/ramstage.h>
-#include <soc/ehci.h>
-
-#include "chip.h"
-
-static const struct reg_script ehci_init_script[] = {
- /* Enable S0 PLL shutdown
- * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */
- REG_PCI_OR16(0x7a, 0x14de),
- /* Enable SB local clock gating
- * D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */
- REG_PCI_OR32(0x7c, 0x0000000c),
- REG_PCI_OR32(0x8c, 0x00000001),
- /* Enable dynamic clock gating 0x4001=0xCE */
- REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE),
- /* Magic RCBA register set sequence */
- /* RCBA + 0x200=0x1 */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001),
- /* RCBA + 0x204=0x2 */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002),
- /* RCBA + 0x208=0x0 */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000),
- /* RCBA + 0x240[4,3,2,1,0]=00000b */
- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0),
- /* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */
- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007),
- /* RCBA + 0x31c[3,2,1,0]=0011b */
- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003),
- REG_SCRIPT_END
-};
-
-static const struct reg_script ehci_clock_gating_script[] = {
- /* Enable SB local clock gating */
- REG_PCI_OR32(0x7c, 0x00004000),
- /* RCBA + 0x284=0xbe (step B0+) */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be),
- REG_SCRIPT_END
-};
-
-static const struct reg_script ehci_disable_script[] = {
- /* Clear Run/Stop Bit */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0),
- /* Wait for HC Halted */
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS,
- USB2STS_HCHALT, USB2STS_HCHALT, 10000),
- /* Disable Interrupts */
- REG_PCI_OR32(EHCI_CMD_STS, INTRDIS),
- /* Disable Asynchronous and Periodic Scheduler */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD,
- ~(USB2CMD_ASE | USB2CMD_PSE), 0),
- /* Disable port wake */
- REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0),
- /* Set Function Disable bit in RCBA */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS),
- REG_SCRIPT_END
-};
-
-static const struct reg_script ehci_hc_reset[] = {
- REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET),
- REG_SCRIPT_END
-};
-
-static void usb2_phy_init(device_t dev)
-{
- struct soc_intel_baytrail_config *config = dev->chip_info;
- u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
- 0x4700 : config->usb2_comp_bg);
- struct reg_script usb2_phy_script[] = {
- /* USB3PHYInit() */
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
- usb2_comp_bg),
- /* Per port phy settings, set in devicetree.cb */
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0,
- config->usb2_per_port_lane0),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY,
- USBPHY_PER_PORT_RCOMP_HS_PULLUP0,
- config->usb2_per_port_rcomp_hs_pullup0),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1,
- config->usb2_per_port_lane1),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY,
- USBPHY_PER_PORT_RCOMP_HS_PULLUP1,
- config->usb2_per_port_rcomp_hs_pullup1),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2,
- config->usb2_per_port_lane2),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY,
- USBPHY_PER_PORT_RCOMP_HS_PULLUP2,
- config->usb2_per_port_rcomp_hs_pullup2),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3,
- config->usb2_per_port_lane3),
- REG_IOSF_WRITE(IOSF_PORT_USBPHY,
- USBPHY_PER_PORT_RCOMP_HS_PULLUP3,
- config->usb2_per_port_rcomp_hs_pullup3),
- REG_SCRIPT_END
- };
- reg_script_run(usb2_phy_script);
-}
-
-static void ehci_init(device_t dev)
-{
- struct soc_intel_baytrail_config *config = dev->chip_info;
- struct reg_script ehci_hc_init[] = {
- /* Controller init */
- REG_SCRIPT_NEXT(ehci_init_script),
- /* Enable clock gating */
- REG_SCRIPT_NEXT(ehci_clock_gating_script),
- /*
- * Disable ports if requested
- */
- /* Open per-port disable control override */
- REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN),
- REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask),
- /* Close per-port disable control override */
- REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0),
- REG_SCRIPT_END
- };
-
- /* Don't reset controller in S3 resume path */
- if (!acpi_is_wakeup_s3())
- reg_script_run_on_dev(dev, ehci_hc_reset);
-
- /* Disable controller if ports are routed to XHCI */
- if (config->usb_route_to_xhci) {
- /* Disable controller */
- reg_script_run_on_dev(dev, ehci_disable_script);
-
- /* Hide device with southcluster function */
- dev->enabled = 0;
- southcluster_enable_dev(dev);
- } else {
- /* Initialize EHCI controller */
- reg_script_run_on_dev(dev, ehci_hc_init);
- }
-
- /* Setup USB2 PHY based on board config */
- usb2_phy_init(dev);
-}
-
-static struct device_operations ehci_device_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ehci_init,
- .ops_pci = &soc_pci_ops,
-};
-
-static const struct pci_driver baytrail_ehci __pci_driver = {
- .ops = &ehci_device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = EHCI_DEVID
-};
diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c
index 4fa92f7..1626d0f 100644
--- a/src/soc/intel/braswell/elog.c
+++ b/src/soc/intel/braswell/elog.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -20,15 +21,15 @@
#include <arch/io.h>
#include <arch/acpi.h>
-#include <stdint.h>
-#include <console/console.h>
#include <cbmem.h>
+#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <elog.h>
#include <soc/iomap.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
+#include <stdint.h>
static void log_power_and_resets(const struct chipset_power_state *ps)
{
@@ -37,29 +38,23 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_PWROK_FAIL);
}
- if (ps->gen_pmcon1 & SUS_PWR_FLR) {
+ if (ps->gen_pmcon1 & SUS_PWR_FLR)
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
- }
- if (ps->gen_pmcon1 & RPS) {
+ if (ps->gen_pmcon1 & RPS)
elog_add_event(ELOG_TYPE_RTC_RESET);
- }
- if (ps->tco_sts & SECOND_TO_STS) {
+ if (ps->tco_sts & SECOND_TO_STS)
elog_add_event(ELOG_TYPE_TCO_RESET);
- }
- if (ps->pm1_sts & PRBTNOR_STS) {
+ if (ps->pm1_sts & PRBTNOR_STS)
elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
- }
- if (ps->gen_pmcon1 & SRS) {
+ if (ps->gen_pmcon1 & SRS)
elog_add_event(ELOG_TYPE_RESET_BUTTON);
- }
- if (ps->gen_pmcon1 & GEN_RST_STS) {
+ if (ps->gen_pmcon1 & GEN_RST_STS)
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
- }
}
static void log_wake_events(const struct chipset_power_state *ps)
@@ -74,33 +69,27 @@ static void log_wake_events(const struct chipset_power_state *ps)
/* Mask off disabled events. */
gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
- if (ps->pm1_sts & WAK_STS) {
+ if (ps->pm1_sts & WAK_STS)
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_is_wakeup_s3() ? 3 : 5);
- }
+ acpi_slp_type == 3 ? 3 : 5);
- if (ps->pm1_sts & PWRBTN_STS) {
+ if (ps->pm1_sts & PWRBTN_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
- }
- if (ps->pm1_sts & RTC_STS) {
+ if (ps->pm1_sts & RTC_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
- }
- if (gpe0_sts & PME_B0_EN) {
+ if (gpe0_sts & PME_B0_EN)
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
- }
- if (gpe0_sts & pcie_wake_mask) {
+ if (gpe0_sts & pcie_wake_mask)
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
- }
gpio_mask = SUS_GPIO_STS0;
i = 0;
while (gpio_mask) {
- if (gpio_mask & gpe0_sts) {
+ if (gpio_mask & gpe0_sts)
elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
- }
gpio_mask <<= 1;
i++;
}
@@ -111,8 +100,8 @@ void southcluster_log_state(void)
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps == NULL) {
- printk(BIOS_DEBUG, "Not logging power state information. "
- "Power state not found in cbmem.\n");
+ printk(BIOS_DEBUG,
+ "Not logging power state information. Power state not found in cbmem.\n");
return;
}
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c
index 3c65de3..7420205 100644
--- a/src/soc/intel/braswell/emmc.c
+++ b/src/soc/intel/braswell/emmc.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -32,46 +33,34 @@
#include "chip.h"
static const struct reg_script emmc_ops[] = {
- /* Enable 2ms card stable feature. */
- REG_PCI_OR32(0xa8, (1 << 24)),
- /* Enable HS200 */
- REG_PCI_WRITE32(0xa0, 0x446cc801),
- REG_PCI_WRITE32(0xa4, 0x80000807),
- /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
- REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
- /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */
- REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
- /* Set slew for HS200 */
- REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
- REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
- /* Max timeout */
- REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
REG_SCRIPT_END,
};
static void emmc_init(device_t dev)
{
- struct soc_intel_baytrail_config *config = dev->chip_info;
+ struct soc_intel_braswell_config *config = dev->chip_info;
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
printk(BIOS_DEBUG, "eMMC init\n");
reg_script_run_on_dev(dev, emmc_ops);
- if (config->scc_acpi_mode)
+ if (config->emmc_acpi_mode) {
+ printk(BIOS_DEBUG, "Enabling ACPI mode\n");
scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC);
+ }
}
-static struct device_operations device_ops = {
+static struct device_operations emmc_device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = emmc_init,
- .enable = NULL,
- .scan_bus = NULL,
.ops_pci = &soc_pci_ops,
};
static const struct pci_driver southcluster __pci_driver = {
- .ops = &device_ops,
+ .ops = &emmc_device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = MMC_DEVID,
};
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index bf38d2e..703746d 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,250 +18,28 @@
* Foundation, Inc.
*/
+#include "chip.h"
#include <arch/io.h>
#include <console/console.h>
-#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <reg_script.h>
-#include <stdlib.h>
-
#include <soc/gfx.h>
-#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-#include "chip.h"
-
-#define GFX_TIMEOUT 100000 /* 100ms */
-
-/*
- * Lock Power Context Base Register to point to a 24KB block
- * of memory in GSM. Power context save data is stored here.
- */
-static void gfx_lock_pcbase(device_t dev)
-{
- struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
- const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
- 288,320,352,384,416,448,480,512 };
- u32 pcsize = 24 << 10; /* 24KB */
- u32 wopcmsz = 0x100000; /* PAVP offset */
- u32 gms, gmsize, pcbase;
-
- gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK;
- gms >>= 3;
- if (gms > ARRAY_SIZE(gms_size_map))
- return;
- gmsize = gms_size_map[gms];
-
- /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */
- pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000;
- pcbase += (gmsize-1) * wopcmsz - pcsize;
- pcbase |= 1; /* Lock */
-
- write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase);
-}
-
-static const struct reg_script gfx_init_script[] = {
- /* Allow-Wake render/media wells */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT),
- /* Render Force-Wake */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000,
- GFX_TIMEOUT),
- /* Media Force-Wake */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000,
- GFX_TIMEOUT),
- /* Workaround - X0:261954/A0:261955 */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1),
-
- /*
- * PowerMeter Weights
- */
-
- /* SET1 */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000),
- /* SET2 */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000),
- /* SET3 */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000),
- /* Enable PowerMeter Counters */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058),
-
- /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
- /* SDP Profile 4 == 0x11940, others 0xcf08 */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
-
- /* GfxPause */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),
-
- /* Dynamic EU Control Settings */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004),
-
- /* Lock ECO Bit Settings */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000),
-
- /* DOP Clock Gating */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001),
-
- /* MBCunit will send the VCR (Fuse) writes as NP-W */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000),
-
- /*
- * RC6 Settings
- */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000),
- /* RC1e - RC6/6p - RC6pp Wake Rate Limits */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019),
- /* RC Sleep / RCx Thresholds */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557),
-
- /*
- * Turbo Settings
- */
-
- /* Render/Video/Blitter Idle Max Count */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A),
- /* RP Down Timeout */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240),
-
- /*
- * Turbo Control Settings
- */
-
- /* RP Up/Down Threshold */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08),
- /* RP Up/Down EI */
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0),
- REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730),
-
- /* RP Idle Hysteresis */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
-
- /* HW RC6 Control Settings */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000),
-
- /* RP Control */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592),
-
- /* Enable PM Interrupts */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e),
-
- /* Aggressive Clock Gating */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0),
-
- /* Enable Gfx Turbo. */
- REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG,
- ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0),
- REG_SCRIPT_END
-};
-
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
- /* Display */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
- REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
- GFX_TIMEOUT),
- /* Tx/Rx Lanes */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0),
- REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0,
- GFX_TIMEOUT),
- /* Common Lane */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0),
- REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0,
- GFX_TIMEOUT),
- /* Ungating Tx only */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0),
- REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0,
- GFX_TIMEOUT),
- /* Ungating Common Lane only */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0),
- REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0,
- GFX_TIMEOUT),
- /* Ungating Display */
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000),
- REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000,
- GFX_TIMEOUT),
REG_SCRIPT_END
};
static const struct reg_script gfx_post_vbios_script[] = {
- /* Deassert Render Force-Wake */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT),
- /* Deassert Media Force-Wake */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000),
- REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT),
/* Set Lock bits */
- REG_PCI_RMW32(GGC, 0xffffffff, 1),
- REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1),
- REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1),
+ REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
+ REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK),
+ REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK),
REG_SCRIPT_END
};
@@ -271,111 +50,28 @@ static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
static void gfx_pre_vbios_init(device_t dev)
{
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
gfx_run_script(dev, gpu_pre_vbios_script);
}
-static void gfx_pm_init(device_t dev)
-{
- printk(BIOS_INFO, "GFX: Power Management Init\n");
- gfx_run_script(dev, gfx_init_script);
-
- /* Lock power context base */
- gfx_lock_pcbase(dev);
-}
-
static void gfx_post_vbios_init(device_t dev)
{
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
gfx_run_script(dev, gfx_post_vbios_script);
}
-static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
-{
- int divider;
- struct resource *res;
-
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
-
- if (res == NULL)
- return;
-
- /* Default to 200 Hz if nothing is set. */
- if (req_hz == 0)
- req_hz = 200;
-
- /* Base clock is 25MHz */
- divider = 25 * 1000 * 1000 / (16 * req_hz);
-
- /* Do not set duty cycle (lower 16 bits). Just set the divider. */
- write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
-}
-
-static void gfx_panel_setup(device_t dev)
-{
- struct soc_intel_baytrail_config *config = dev->chip_info;
- struct reg_script gfx_pipea_init[] = {
- /* CONTROL */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
- PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
- /* POWER ON */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS),
- (config->gpu_pipea_port_select << 30 |
- config->gpu_pipea_power_on_delay << 16 |
- config->gpu_pipea_light_on_delay)),
- /* POWER OFF */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS),
- (config->gpu_pipea_power_off_delay << 16 |
- config->gpu_pipea_light_off_delay)),
- /* DIVISOR */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR),
- ~0x1f, config->gpu_pipea_power_cycle_delay),
- REG_SCRIPT_END
- };
- struct reg_script gfx_pipeb_init[] = {
- /* CONTROL */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL),
- PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
- /* POWER ON */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS),
- (config->gpu_pipeb_port_select << 30 |
- config->gpu_pipeb_power_on_delay << 16 |
- config->gpu_pipeb_light_on_delay)),
- /* POWER OFF */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS),
- (config->gpu_pipeb_power_off_delay << 16 |
- config->gpu_pipeb_light_off_delay)),
- /* DIVISOR */
- REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR),
- ~0x1f, config->gpu_pipeb_power_cycle_delay),
- REG_SCRIPT_END
- };
-
- if (config->gpu_pipea_port_select) {
- printk(BIOS_INFO, "GFX: Initialize PIPEA\n");
- reg_script_run_on_dev(dev, gfx_pipea_init);
- set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL),
- config->gpu_pipea_pwm_freq_hz);
- }
-
- if (config->gpu_pipeb_port_select) {
- printk(BIOS_INFO, "GFX: Initialize PIPEB\n");
- reg_script_run_on_dev(dev, gfx_pipeb_init);
- set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL),
- config->gpu_pipeb_pwm_freq_hz);
- }
-}
-
static void gfx_init(device_t dev)
{
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
+
/* Pre VBIOS Init */
gfx_pre_vbios_init(dev);
- /* Power Management Init */
- gfx_pm_init(dev);
-
- gfx_panel_setup(dev);
-
/* Run VBIOS */
pci_dev_init(dev);
@@ -383,8 +79,28 @@ static void gfx_init(device_t dev)
gfx_post_vbios_init(dev);
}
+static void gfx_read_resources(device_t dev)
+{
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
+
+ pci_dev_read_resources(dev);
+
+#if IS_ENABLED(CONFIG_MARK_GRAPHICS_MEM_WRCOMB)
+ struct resource *res;
+
+ /* Set the graphics memory to write combining. */
+ res = find_resource(dev, PCI_BASE_ADDRESS_2);
+ if (res == NULL) {
+ printk(BIOS_DEBUG, "GFX: memory resource not found.\n");
+ return;
+ }
+ res->flags |= IORESOURCE_WRCOMB;
+#endif
+}
+
static struct device_operations gfx_device_ops = {
- .read_resources = pci_dev_read_resources,
+ .read_resources = gfx_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gfx_init,
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c
old mode 100644
new mode 100755
index 0c32917..637a4da
--- a/src/soc/intel/braswell/gpio.c
+++ b/src/soc/intel/braswell/gpio.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,228 +18,298 @@
* Foundation, Inc.
*/
-#include <device/pci.h>
+
#include <console/console.h>
+#include <device/pci.h>
#include <soc/gpio.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
#include <soc/smm.h>
-/* GPIO-to-Pad LUTs */
-static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
- { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
- 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
- 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
- 2, 5, 9 }; /* [24:26] */
-
-static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
- { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
- 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
- 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
- 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
- 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
- 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
- 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
- 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
- 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
- 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
- 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
- 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
- 106, 87, 91, 104, 97, 100 }; /* [96:101] */
-
-static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
- { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
- 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
- 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
- 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
- 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
- 52, 53, 59, 40 }; /* [40:43] */
-
-/* GPIO bank descriptions */
-static const struct gpio_bank gpncore_bank = {
- .gpio_count = GPNCORE_COUNT,
- .gpio_to_pad = gpncore_gpio_to_pad,
- .legacy_base = GP_LEGACY_BASE_NONE,
- .pad_base = GPNCORE_PAD_BASE,
- .has_wake_en = 0,
- .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
- .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
+
+#define GPIO_DEBUG
+
+/* gpio map to pad number LUTs */
+
+static const u8 gpncommunity_gpio_to_pad[GP_NORTH_COUNT] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+ 26, 27, 30, 31, 32, 33, 34, 35, 36, 37,
+ 38, 39, 40, 41, 45, 46, 47, 48, 49, 50,
+ 51, 52, 53, 54, 55, 56, 60, 61, 62, 63,
+ 64, 65, 66, 67, 68, 69, 70, 71, 72 };
+
+static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 15, 16,
+ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+ 30, 31, 32, 33, 34, 35, 45, 46, 47, 48,
+ 49, 50, 51, 52, 60, 61, 62, 63, 64, 65,
+ 66, 67, 68, 69, 75, 76, 77, 78, 79, 80,
+ 81, 82, 83, 84, 85 };
+
+
+static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 15, 16,
+ 17, 18, 19, 20, 21, 22, 30, 31, 32, 33,
+ 34, 35, 36, 37, 45, 46, 47, 48, 49, 50,
+ 51, 52, 60, 61, 62, 63, 64, 65, 66, 67,
+ 75, 76, 77, 78, 79, 80, 81, 82, 90, 91,
+ 92, 93, 94, 95, 96, 97 };
+
+static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
+ 10, 11, 15, 16, 17, 18, 19, 20, 21, 22,
+ 23, 24, 25, 26 };
+
+/* GPIO Community descriptions */
+static const struct gpio_bank gpnorth_community = {
+ .gpio_count = GP_NORTH_COUNT,
+ .gpio_to_pad = gpncommunity_gpio_to_pad ,
+ .pad_base = COMMUNITY_GPNORTH_BASE ,
+ .has_gpe_en = GPE_CAPABLE ,
+ .has_wake_en = 1,
};
-static const struct gpio_bank gpscore_bank = {
- .gpio_count = GPSCORE_COUNT,
- .gpio_to_pad = gpscore_gpio_to_pad,
- .legacy_base = GPSCORE_LEGACY_BASE,
- .pad_base = GPSCORE_PAD_BASE,
- .has_wake_en = 0,
- .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
- .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
+static const struct gpio_bank gpsoutheast_community = {
+ .gpio_count = GP_SOUTHEAST_COUNT,
+ .gpio_to_pad = gpsecommunity_gpio_to_pad,
+ .pad_base = COMMUNITY_GPSOUTHEAST_BASE,
+ .has_gpe_en = GPE_CAPABLE_NONE,
+ .has_wake_en = 1,
};
-static const struct gpio_bank gpssus_bank = {
- .gpio_count = GPSSUS_COUNT,
- .gpio_to_pad = gpssus_gpio_to_pad,
- .legacy_base = GPSSUS_LEGACY_BASE,
- .pad_base = GPSSUS_PAD_BASE,
+static const struct gpio_bank gpsouthwest_community = {
+ .gpio_count = GP_SOUTHWEST_COUNT,
+ .gpio_to_pad = gpswcommunity_gpio_to_pad,
+ .pad_base = COMMUNITY_GPSOUTHWEST_BASE,
+ .has_gpe_en = GPE_CAPABLE,
.has_wake_en = 1,
- .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START,
- .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END,
};
+static const struct gpio_bank gpeast_community = {
+ .gpio_count = GP_EAST_COUNT,
+ .gpio_to_pad = gpecommunity_gpio_to_pad,
+ .pad_base = COMMUNITY_GPEAST_BASE,
+ .has_gpe_en = GPE_CAPABLE_NONE,
+ .has_wake_en = 1,
+};
+
+static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
+ const struct soc_gpio_map *n_gpios)
+{
+ const struct soc_gpio_map *n_config;
+ const struct soc_gpio_map *sw_config;
+ uint32_t route_reg = 0;
+ uint32_t int_selection = 0;
+ uint32_t alt_gpio_smi = 0;
+ uint32_t gpe0a_en = 0;
+ int gpio = 0;
+ int north_done = 0;
+ int south_done = 0;
+
+ for (sw_config = sw_gpios, n_config = n_gpios;
+ (!north_done || !south_done); sw_config++, n_config++, gpio++) {
+
+ /* when north config is done */
+ if ((gpio > GP_NORTH_COUNT) ||
+ (n_config->pad_conf0 == GPIO_LIST_END))
+ north_done = 1;
+
+ /* when sw is done */
+ if ((gpio > GP_SOUTHWEST_COUNT) ||
+ (sw_config->pad_conf0 == GPIO_LIST_END))
+ south_done = 1;
+
+ /* route north gpios */
+ if (!north_done) {
+ /* Int select from 8 to 15 */
+ int_selection = ((n_config->pad_conf0 >> 28) & 0xf);
+ if (n_config->gpe == SMI) {
+ /*
+ * Set the corresponding bits (01) as
+ * per the interrupt line
+ */
+ route_reg |= (1 << ((int_selection - 8) * 2));
+ /* reset the higher bit */
+ route_reg &=
+ ~(1 << ((int_selection - 8) * 2 + 1));
+ alt_gpio_smi |= (1 << (int_selection + 8));
+ } else if (n_config->gpe == SCI) {
+ /*
+ * Set the corresponding bits as per the
+ * interrupt line
+ */
+ route_reg |=
+ (1 << (((int_selection - 8) * 2) + 1));
+ /* reset the bit */
+ route_reg &= ~(1 << ((int_selection - 8) * 2));
+ gpe0a_en |= (1 << (int_selection + 8));
+ }
+ }
+
+ /* route southwest gpios */
+ if (!south_done) {
+ /* Int select from 8 to 15 */
+ int_selection = ((sw_config->pad_conf0 >> 28) & 0xf);
+ if (sw_config->gpe == SMI) {
+ /*
+ * Set the corresponding bits (10) as
+ * per the interrupt line
+ */
+ route_reg |= (1 << (int_selection * 2));
+ route_reg &= ~(1 << (int_selection * 2 + 1));
+ alt_gpio_smi |= (1 << (int_selection + 16));
+ } else if (sw_config->gpe == SCI) {
+ /*
+ * Set the corresponding bits as
+ * per the interrupt line
+ */
+ route_reg |= (1 << ((int_selection * 2) + 1));
+ /* reset the bit */
+ route_reg &= ~(1 << (int_selection * 2));
+ gpe0a_en |= (1 << (int_selection + 16));
+ }
+ }
+ }
+
+ /* enable gpe bits in GPE0A_EN_REG */
+ outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG);
+
+#ifdef GPIO_DEBUG
+ printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n",
+ route_reg, alt_gpio_smi, gpe0a_en);
+#endif
+ /* Save as an smm param */
+ southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
+}
+
+
static void setup_gpios(const struct soc_gpio_map *gpios,
- const struct gpio_bank *bank)
+ const struct gpio_bank *community)
{
const struct soc_gpio_map *config;
int gpio = 0;
- u32 reg, pad_conf0;
- u8 set, bit;
-
- u32 use_sel[4] = {0};
- u32 io_sel[4] = {0};
- u32 gp_lvl[4] = {0};
- u32 tpe[4] = {0};
- u32 tne[4] = {0};
- u32 wake_en[4] = {0};
+ u32 reg, family, internal_pad_num;
+ u32 mmio_addr, int_selection;
+ u32 gpio_wake0 = 0;
+ u32 gpio_wake1 = 0;
+ u32 gpio_int_mask = 0;
if (!gpios)
return;
-
for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
config++, gpio++) {
- if (gpio > bank->gpio_count)
+ if (gpio > community->gpio_count)
break;
- set = gpio >> 5;
- bit = gpio % 32;
-
- if (bank->legacy_base != GP_LEGACY_BASE_NONE) {
- /* Legacy IO configuration */
- use_sel[set] |= config->use_sel << bit;
- io_sel[set] |= config->io_sel << bit;
- gp_lvl[set] |= config->gp_lvl << bit;
- tpe[set] |= config->tpe << bit;
- tne[set] |= config->tne << bit;
-
- /* Some banks do not have wake_en ability */
- if (bank->has_wake_en)
- wake_en[set] |= config->wake_en << bit;
- }
-
/* Pad configuration registers */
- reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
-
- /* Add correct func to GPIO pad config */
- pad_conf0 = config->pad_conf0;
- if (config->is_gpio)
- {
- if (gpio >= bank->gpio_f1_range_start &&
- gpio <= bank->gpio_f1_range_end)
- pad_conf0 |= PAD_FUNC1;
- else
- pad_conf0 |= PAD_FUNC0;
- }
-
+ family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO;
+ internal_pad_num = community->gpio_to_pad[gpio] %
+ MAX_FAMILY_PAD_GPIO_NO;
+
+ /*
+ * Calculate the MMIO Address for specific GPIO pin
+ * control register pointed by index.
+ * REG = (IOBASE + COMMUNITY_BASE + (0X04400)) +
+ * (0X400*FAMILY_NUM) + (8 * PAD_NUM)
+ */
+ mmio_addr = FAMILY_PAD_REGS_OFF
+ + (FAMILY_PAD_REGS_SIZE * family)
+ + (GPIO_REGS_SIZE * internal_pad_num);
+
+ reg = community->pad_base + mmio_addr;
+
+ /* get int selection value */
+ int_selection = ((config->pad_conf0 >> 28) & 0xf);
+
+ /* get int mask register value */
+ gpio_int_mask |= (config->int_mask << int_selection);
+
+ /*
+ * wake capable programming
+ * some communities have 2 wake regs
+ */
+ if (gpio > 31)
+ gpio_wake1 |= config->wake_mask << (gpio % 32);
+ else
+ gpio_wake0 |= config->wake_mask << gpio;
+
+ if (!config->skip_config) {
#ifdef GPIO_DEBUG
- printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
- reg, pad_conf0, config->pad_conf1, config->pad_val);
+ printk(BIOS_DEBUG,
+ "Write Pad: Base(%x) - conf0 = %x conf1= %x gpio #- %d pad # = %d\n",
+ reg, config->pad_conf0, config->pad_conf1,
+ community->gpio_to_pad[gpio], gpio);
#endif
-
- write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0);
- write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1);
- write32((u32 *)(reg + PAD_VAL_REG), config->pad_val);
+ /*
+ * write pad configurations to conf0 and conf1 register
+ */
+ write32((void *)(reg + PAD_CONF0_REG),
+ config->pad_conf0);
+ write32((void *)(reg + PAD_CONF1_REG),
+ config->pad_conf1);
+ }
}
- if (bank->legacy_base != GP_LEGACY_BASE_NONE)
- for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) {
- reg = bank->legacy_base + 0x20 * set;
-
#ifdef GPIO_DEBUG
- printk(BIOS_DEBUG,
- "Write GPIO: Reg(%x) - %x %x %x %x %x\n",
- reg, use_sel[set], io_sel[set], gp_lvl[set],
- tpe[set], tne[set]);
+ printk(BIOS_DEBUG,
+ "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n",
+ gpio_wake0, gpio_wake1, gpio_int_mask);
#endif
- outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
- outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
- outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
- outl(tpe[set], reg + LEGACY_TPE_REG);
- outl(tne[set], reg + LEGACY_TNE_REG);
+ /* Wake */
+ write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0),
+ gpio_wake0);
- /* TS registers are WOC */
- outl(0, reg + LEGACY_TS_REG);
+ /* wake mask config for communities with 2 regs */
+ if (community->gpio_count > 32)
+ write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1),
+ gpio_wake1);
- if (bank->has_wake_en)
- outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
- }
-}
+ /* Interrupt */
+ write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK),
+ gpio_int_mask);
-static void setup_gpio_route(const struct soc_gpio_map *sus,
- const struct soc_gpio_map *core)
-{
- uint32_t route_reg = 0;
- int i;
-
- for (i = 0; i < 8; i++) {
- /* SMI takes precedence and wake_en implies SCI. */
- if (sus[i].smi) {
- route_reg |= ROUTE_SMI << (2 * i);
- } else if (sus[i].sci) {
- route_reg |= ROUTE_SCI << (2 * i);
- }
-
- if (core[i].smi) {
- route_reg |= ROUTE_SMI << (2 * (i + 8));
- } else if (core[i].sci) {
- route_reg |= ROUTE_SCI << (2 * (i + 8));
- }
- }
- southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
}
-static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
- const struct gpio_bank *bank)
-{
- u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
- u32 val;
- int i;
-
- /* Write all four DIRQ registers */
- for (i=0; i<4; ++i) {
- val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
- dirq[i * 4 + 1] << 8 | dirq[i * 4];
- write32(reg + i, val);
-#ifdef GPIO_DEBUG
- printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
- reg + i, val);
-#endif
- }
-}
void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
{
+
if (config) {
- setup_gpios(config->ncore, &gpncore_bank);
- setup_gpios(config->score, &gpscore_bank);
- setup_gpios(config->ssus, &gpssus_bank);
- setup_gpio_route(config->ssus, config->score);
-
- if (config->core_dirq)
- setup_dirqs(*config->core_dirq, &gpscore_bank);
- if (config->sus_dirq)
- setup_dirqs(*config->sus_dirq, &gpssus_bank);
+
+ /*
+ * Write the default value 0xffffff to the SW
+ * write_access_policy_interrupt_reg to allow the SW interrupt
+ * mask register to be set
+ */
+ write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108),
+ 0xffffffff);
+
+ printk(BIOS_DEBUG, "north\n");
+ setup_gpios(config->north, &gpnorth_community);
+
+ printk(BIOS_DEBUG, "southwest\n");
+ setup_gpios(config->southwest, &gpsouthwest_community);
+
+ printk(BIOS_DEBUG, "southeast\n");
+ setup_gpios(config->southeast, &gpsoutheast_community);
+
+ printk(BIOS_DEBUG, "east\n");
+ setup_gpios(config->east, &gpeast_community);
+
+ printk(BIOS_DEBUG, "Routing SW and N gpios\n");
+ setup_gpio_route(config->southwest, config->north);
}
- /* Set on die termination feature with pull up value and
+ /*
+ * Set on die termination feature with pull up value and
* drive the pad high for TAP_TDO and TAP_TMS
*/
- if (!enable_xdp_tap) {
+ if (!enable_xdp_tap)
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
- write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc);
- write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc);
- }
}
-struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)
+__attribute__((weak)) struct soc_gpio_config *mainboard_get_gpios(void)
{
printk(BIOS_DEBUG, "Default/empty GPIO config\n");
return NULL;
diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c
new file mode 100644
index 0000000..7be1914
--- /dev/null
+++ b/src/soc/intel/braswell/gpio_support.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/console.h>
+#include <soc/gpio.h>
+
+/*
+ * Return family number and internal pad number in that community by pad number
+ * and which community it is in.
+ */
+uint16_t gpio_family_number(uint8_t community, uint8_t pad)
+{
+ /*
+ * Refer to BSW BIOS Writers Guide, Table "Family Number".
+ * BSW has 4 GPIO communities. Each community has up to 7 families and
+ * each family contains a range of Pad numbers. The number in the array
+ * is the maximum no. of that range.
+ * For example: East community, family 0, Pad 0~11.
+ */
+ static const uint8_t community_base[GPIO_COMMUNITY_COUNT]
+ [GPIO_FAMILIES_MAX_PER_COMM + 1] = {
+ {0, 8, 16, 24, 32, 40, 48, 56}, /* Southwest */
+ {0, 9, 22, 34, 46, 59, 59, 59}, /* North */
+ {0, 12, 24, 24, 24, 24, 24, 24}, /* East */
+ {0, 8, 20, 26, 34, 44, 55, 55} /* Southeast */
+ };
+ const uint8_t *base;
+ uint8_t i;
+
+ /* Validate the pad number */
+ if (pad > community_base[community][7])
+ die("Pad number is out of range!");
+
+ /* Locate the family number for the pad */
+ base = &community_base[community][0];
+ for (i = 0; i < 7; i++) {
+ if ((pad >= base[0]) && (pad < base[1]))
+ break;
+ base++;
+ }
+
+ /* Family number in high byte and inner pad number in lowest byte */
+ return (i << 8) + pad - *base;
+}
+
+/*
+ * Return pad configuration register offset by pad number and which community
+ * it is in.
+ */
+uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad)
+{
+ uint16_t fpad;
+ uint32_t *pad_config_reg;
+
+ /* Get the GPIO family number */
+ fpad = gpio_family_number(community, pad);
+
+ /*
+ * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space
+ * Registers Addresses" for the Pad configuration register calculation.
+ */
+ pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + 0x4400 +
+ (0x400 * (fpad >> 8)) + (8 * (fpad & 0xff)));
+
+ return pad_config_reg;
+}
+
+int get_gpio(int community_base, int pad0_offset)
+{
+ return (read32((void *)(community_base + pad0_offset))) & PAD_RX_BIT;
+}
diff --git a/src/soc/intel/braswell/hda.c b/src/soc/intel/braswell/hda.c
index f20386f..31593fd 100644
--- a/src/soc/intel/braswell/hda.c
+++ b/src/soc/intel/braswell/hda.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,88 +25,16 @@
#include <device/pci_ids.h>
#include <reg_script.h>
-#include <soc/intel/common/hda_verb.h>
+#include <soc/hda.h>
#include <soc/iomap.h>
-#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
-static const struct reg_script init_ops[] = {
- /* Enable no snoop traffic. */
- REG_PCI_OR16(0x78, 1 << 11),
- /* Configure HDMI codec connection. */
- REG_PCI_OR32(0xc4, 1 << 1),
- REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
- REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
- /* Configure internal settings. */
- REG_PCI_OR32(0xc0, 0x7 << 21),
- REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
- REG_PCI_WRITE32(0xc8, 0x82a30000),
- REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
- /* Disable docking. */
- REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
- REG_SCRIPT_END,
-};
-
-static const uint32_t hdmi_codec_verb_table[] = {
- /* coreboot specific header */
- 0x80862882, /* vid did for hdmi codec */
- 0x00000000, /* subsystem id */
- 0x00000003, /* number of jacks */
-
- /* pin widget 5 - port B */
- 0x20471c10,
- 0x20471d00,
- 0x20471e56,
- 0x20471f18,
-
- /* pin widget 6 - port C */
- 0x20571c20,
- 0x20571d00,
- 0x20571e56,
- 0x20571f18,
-
- /* pin widget 7 - port D */
- 0x20671c30,
- 0x20671d00,
- 0x20671e56,
- 0x20671f58,
-};
-
-static void hda_init(device_t dev)
-{
- struct resource *res;
- int codec_mask;
- int i;
- u8 *base;
-
- reg_script_run_on_dev(dev, init_ops);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res == NULL)
- return;
-
- base = res2mmio(res, 0, 0);
- codec_mask = hda_codec_detect(base);
-
- printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
- if (!codec_mask)
- return;
-
- for (i = 3; i >= 0; i--) {
- if (!((1 << i) & codec_mask))
- continue;
- hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
- hdmi_codec_verb_table);
- }
-}
-
static const struct device_operations device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = hda_init,
+ .init = NULL,
.enable = NULL,
.scan_bus = NULL,
.ops_pci = &soc_pci_ops,
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index fb88d12..7f0d5d8 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -2,13 +2,14 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
@@ -17,15 +18,21 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_ACPI_H_
-#define _BAYTRAIL_ACPI_H_
+#ifndef _SOC_ACPI_H_
+#define _SOC_ACPI_H_
#include <arch/acpi.h>
#include <soc/nvs.h>
-void acpi_create_intel_hpet(acpi_hpet_t * hpet);
+#if CONFIG_GOP_SUPPORT
+#include <soc/intel/common/gma.h>
+int init_igd_opregion(igd_opregion_t *igd_opregion);
+#endif
+
+void acpi_create_intel_hpet(acpi_hpet_t *hpet);
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
-#endif /* _BAYTRAIL_ACPI_H_ */
+#endif /* _SOC_ACPI_H_ */
+
diff --git a/src/soc/intel/braswell/include/soc/chipset_fsp_util.h b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
new file mode 100644
index 0000000..c269a61
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/chipset_fsp_util.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef CHIPSET_FSP_UTIL_H
+#define CHIPSET_FSP_UTIL_H
+
+/*
+ * Include the FSP binary interface files
+ *
+ * These files include the necessary UEFI constants and data structures
+ * that are used to interface to the FSP binary.
+ */
+
+#include <uefi_types.h> /* UEFI data types */
+#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */
+#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */
+#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */
+#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */
+#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */
+#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */
+#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */
+#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */
+#include <FspUpdVpd.h> /* Vital/updatable product data definitions */
+
+#endif /* CHIPSET_FSP_UTIL_H */
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 719c0f3..18aaf7a 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,8 +18,8 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_DEVICE_NVS_H_
-#define _BAYTRAIL_DEVICE_NVS_H_
+#ifndef _SOC_DEVICE_NVS_H_
+#define _SOC_DEVICE_NVS_H_
#include <stdint.h>
@@ -62,7 +63,6 @@ typedef struct {
/* Extra */
u32 lpe_fw; /* LPE Firmware */
- u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */
} __attribute__((packed)) device_nvs_t;
-#endif
+#endif /* _SOC_DEVICE_NVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/efi_wrapper.h b/src/soc/intel/braswell/include/soc/efi_wrapper.h
deleted file mode 100644
index 3304d03..0000000
--- a/src/soc/intel/braswell/include/soc/efi_wrapper.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * PEI EFI entry point
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Google Inc. nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __EFI_WRAPPER_H__
-#define __EFI_WRAPPER_H__
-
-#define EFI_WRAPPER_VER 2
-
-/* Provide generic x86 calling conventions. */
-#define ABI_X86 __attribute((regparm(0)))
-
-/* Errors returned by the EFI wrapper. */
-enum efi_wrapper_error {
- INVALID_VER = -1,
-};
-
-struct efi_wrapper_params {
- /* Mainboard Inputs */
- int version;
-
- void ABI_X86 (*console_out)(unsigned char byte);
-
- unsigned int tsc_ticks_per_microsecond;
-} __attribute__((packed));
-
-typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *);
-#endif
diff --git a/src/soc/intel/braswell/include/soc/ehci.h b/src/soc/intel/braswell/include/soc/ehci.h
index 444e8ce..22337bf 100644
--- a/src/soc/intel/braswell/include/soc/ehci.h
+++ b/src/soc/intel/braswell/include/soc/ehci.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,28 +18,11 @@
* Foundation, Inc.
*/
-#ifndef BAYTRAIL_EHCI_H
-#define BAYTRAIL_EHCI_H
+#ifndef _SOC_EHCI_H_
+#define _SOC_EHCI_H_
/* EHCI PCI Registers */
#define EHCI_CMD_STS 0x04
# define INTRDIS (1 << 10)
-#define EHCI_SBRN_FLA_PWC 0x60
-# define PORTWKIMP (1 << 16)
-# define PORTWKCAPMASK (0x3ff << 17)
-#define EHCI_USB2PDO 0x64
-/* EHCI Memory Registers */
-#define USB2CMD 0x20
-# define USB2CMD_ASE (1 << 5)
-# define USB2CMD_PSE (1 << 4)
-# define USB2CMD_HCRESET (1 << 1)
-# define USB2CMD_RS (1 << 0)
-#define USB2STS 0x24
-# define USB2STS_HCHALT (1 << 12)
-
-/* RCBA EHCI Registers */
-#define RCBA_FUNC_DIS 0x220
-# define RCBA_EHCI_DIS (1 << 0)
-
-#endif /* BAYTRAIL_EHCI_H */
+#endif /* _SOC_EHCI_H_ */
diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h
index 3b66870..743a89a 100644
--- a/src/soc/intel/braswell/include/soc/gfx.h
+++ b/src/soc/intel/braswell/include/soc/gfx.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,27 +18,48 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_GFX_H_
-#define _BAYTRAIL_GFX_H_
+#ifndef _SOC_GFX_H_
+#define _SOC_GFX_H_
/*
* PCI config registers.
*/
#define GGC 0x50
-# define GGC_VGA_DISABLE (1 << 1)
-# define GGC_GTT_SIZE_MASK (3 << 8)
+# define GGC_VAMEN (1 << 14) /* Enable acceleration mode */
+# define GGC_GTT_SIZE_MASK (3 << 8) /* GTT graphics memory size */
# define GGC_GTT_SIZE_0MB (0 << 8)
-# define GGC_GTT_SIZE_1MB (1 << 8)
-# define GGC_GTT_SIZE_2MB (2 << 8)
-# define GGC_GSM_SIZE_MASK (0x1f << 3)
+# define GGC_GTT_SIZE_2MB (1 << 8)
+# define GGC_GTT_SIZE_4MB (2 << 8)
+# define GGC_GTT_SIZE_8MB (3 << 8)
+# define GGC_GSM_SIZE_MASK (0x1f << 3) /* Main memory use */
# define GGC_GSM_SIZE_0MB (0 << 3)
# define GGC_GSM_SIZE_32MB (1 << 3)
# define GGC_GSM_SIZE_64MB (2 << 3)
+# define GCC_GSM_SIZE_96MB (3 << 3)
# define GGC_GSM_SIZE_128MB (4 << 3)
+# define GGC_GSM_SIZE_160MB (5 << 3)
+# define GGC_GSM_SIZE_192MB (6 << 3)
+# define GGC_GSM_SIZE_224MB (7 << 3)
+# define GGC_GSM_SIZE_256MB (8 << 3)
+# define GGC_GSM_SIZE_288MB (9 << 3)
+# define GGC_GSM_SIZE_320MB (0x0a << 3)
+# define GGC_GSM_SIZE_352MB (0x0b << 3)
+# define GGC_GSM_SIZE_384MB (0x0c << 3)
+# define GGC_GSM_SIZE_416MB (0x0d << 3)
+# define GGC_GSM_SIZE_448MB (0x0e << 3)
+# define GGC_GSM_SIZE_480MB (0x0f << 3)
+# define GGC_GSM_SIZE_512MB (0x10 << 3)
+# define GGC_VGA_DISABLE (1 << 1) /* VGA Disable */
+# define GGC_GGCLCK (1 << 0) /* Prevent register writes */
#define GSM_BASE 0x5c
+# define GSM_BDSM 0xfff00000 /* Base of stolen memory */
+# define GSM_BDSM_LOCK (1 << 0) /* Prevent register writes */
+
#define GTT_BASE 0x70
+# define GTT_BGSM 0xfff00000 /* Base of stolen memory */
+# define GTT_BGSM_LOCK (1 << 0) /* Prevent register writes */
#define MSAC 0x62
#define APERTURE_SIZE_MASK (3 << 1)
@@ -45,20 +67,32 @@
#define APERTURE_SIZE_256MB (1 << 1)
#define APERTURE_SIZE_512MB (3 << 1)
-#define VLV_DISPLAY_BASE 0x180000
-#define PIPEA_REG(reg) (VLV_DISPLAY_BASE + (reg))
-#define PIPEB_REG(reg) (VLV_DISPLAY_BASE + 0x100 + (reg))
+#define SWSCI 0xe8 /* SWSCI enable */
+#define ASLS 0xfc /* OpRegion Base */
/* Panel control registers */
#define HOTPLUG_CTRL 0x61110
#define PP_CONTROL 0x61204
-#define PP_CONTROL_UNLOCK 0xabcd0000
-#define PP_CONTROL_EDP_FORCE_VDD (1 << 3)
+# define PP_CONTROL_WRITE_PROTECT_KEY 0xffff0000 /* Enable display port VDD */
+# define PP_CONTROL_UNLOCK 0xabcd0000
+# define PP_CONTROL_EDP_FORCE_VDD (1 << 3) /* Enable display port VDD */
+# define PP_CONTROL_BACKLIGHT_ENABLE (1 << 2)
+# define PP_CONTROL_POWER_DOWN_ON_RESET (1 << 1)
+# define PP_CONTROL_POWER_STATE_TARGET (1 << 0) /* Power up/down (1/0) */
+
#define PP_ON_DELAYS 0x61208
#define PP_OFF_DELAYS 0x6120c
#define PP_DIVISOR 0x61210
#define BACKLIGHT_CTL2 0x61250
-#define BACKLIGHT_ENABLE (1 << 31)
+# define BACKLIGHT_PWM_ENABLE (1 << 31)
+# define BACKLIGHT_POLARITY (1 << 28) /* Active low/high (1/0) */
+# define BACKLIGHT_PHASE_IN_INT_STATUS (1 << 26)
+# define BACKLIGHT_PHASE_IN_ENABLE (1 << 25)
+# define BACKLIGHT_PHASE_IN_INT_ENABLE (1 << 24)
+# define BACKLIGHT_PHASE_IN_TIME_BASE 0x00ff0000
+# define BACKLIGHT_PHASE_IN_COUNT 0x0000ff00
+# define BACKLIGHT_PHASE_IN_INCREMENT 0x000000ff
+
#define BACKLIGHT_CTL 0x61254
-#endif /* _BAYTRAIL_GFX_H_ */
+#endif /* _SOC_GFX_H_ */
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index fb0b5d2..20a4d51 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,299 +18,332 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_GPIO_H_
-#define _BAYTRAIL_GPIO_H_
+#ifndef _SOC_GPIO_H_
+#define _SOC_GPIO_H_
#include <stdint.h>
#include <arch/io.h>
#include <soc/iomap.h>
-/* #define GPIO_DEBUG */
+#define COMMUNITY_SIZE 0x20000
-/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */
-#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
-#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE)
-#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS)
+#define COMMUNITY_GPSOUTHWEST_BASE \
+(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHWEST)
-/* DIRQ registers start at pad base + 0x980 */
-#define PAD_BASE_DIRQ_OFFSET 0x980
+#define COMMUNITY_GPNORTH_BASE \
+(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH)
-/* Pad register offset */
-#define PAD_CONF0_REG 0x0
-#define PAD_CONF1_REG 0x4
-#define PAD_VAL_REG 0x8
-
-/* Legacy IO register base */
-#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00)
-#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80)
-/* Some banks have no legacy GPIO interface */
-#define GP_LEGACY_BASE_NONE 0xFFFF
-
-#define LEGACY_USE_SEL_REG 0x00
-#define LEGACY_IO_SEL_REG 0x04
-#define LEGACY_GP_LVL_REG 0x08
-#define LEGACY_TPE_REG 0x0C
-#define LEGACY_TNE_REG 0x10
-#define LEGACY_TS_REG 0x14
-#define LEGACY_WAKE_EN_REG 0x18
-
-/* Number of GPIOs in each bank */
-#define GPNCORE_COUNT 27
-#define GPSCORE_COUNT 102
-#define GPSSUS_COUNT 44
-
-/* GPIO legacy IO register settings */
-#define GPIO_USE_MMIO 0
-#define GPIO_USE_LEGACY 1
-
-#define GPIO_DIR_OUTPUT 0
-#define GPIO_DIR_INPUT 1
-
-#define GPIO_LEVEL_LOW 0
-#define GPIO_LEVEL_HIGH 1
-
-#define GPIO_PEDGE_DISABLE 0
-#define GPIO_PEDGE_ENABLE 1
-
-#define GPIO_NEDGE_DISABLE 0
-#define GPIO_NEDGE_ENABLE 1
+#define COMMUNITY_GPEAST_BASE \
+(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPEAST)
-/* config0[29] - Disable second mask */
-#define PAD_MASK2_DISABLE (1 << 29)
+#define COMMUNITY_GPSOUTHEAST_BASE \
+(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHEAST)
-/* config0[27] - Direct Irq En */
-#define PAD_IRQ_EN (1 << 27)
+#define GPIO_COMMUNITY_COUNT 4
+#define GPIO_FAMILIES_MAX_PER_COMM 7
+#define GP_SOUTHWEST 0
+#define GP_NORTH 1
+#define GP_EAST 2
+#define GP_SOUTHEAST 3
-/* config0[26] - gd_tne */
-#define PAD_TNE_IRQ (1 << 26)
+#define COMMUNITY_BASE(community) \
+(IO_BASE_ADDRESS + community * 0x8000)
-/* config0[25] - gd_tpe */
-#define PAD_TPE_IRQ (1 << 25)
+#define GP_READ_ACCESS_POLICY_BASE(community) \
+(COMMUNITY_BASE(community) + 0x000)
-/* config0[24] - Gd Level */
-#define PAD_LEVEL_IRQ (1 << 24)
-#define PAD_EDGE_IRQ (0 << 24)
+#define GP_WRITE_ACCESS_POLICY_BASE(community) \
+(COMMUNITY_BASE(community) + 0x100)
-/* config0[17] - Slow clkgate / glitch filter */
-#define PAD_SLOWGF_ENABLE (1 << 17)
+#define GP_WAKE_STATUS_REG_BASE(community) \
+(COMMUNITY_BASE(community) + 0x200)
-/* config0[16] - Fast clkgate / glitch filter */
-#define PAD_FASTGF_ENABLE (1 << 16)
+#define GP_WAKE_MASK_REG_BASE(community) \
+(COMMUNITY_BASE(community) + 0x280)
-/* config0[15] - Hysteresis enable (inverted) */
-#define PAD_HYST_DISABLE (1 << 15)
-#define PAD_HYST_ENABLE (0 << 15)
+#define GP_INT_STATUS_REG_BASE(community) \
+(COMMUNITY_BASE(community) + 0x300)
-/* config0[14:13] - Hysteresis control */
-#define PAD_HYST_CTRL_DEFAULT (2 << 13)
+#define GP_INT_MASK_REG_BASE(community) \
+(COMMUNITY_BASE(community) + 0x380)
-/* config0[11] - Bypass Flop */
-#define PAD_FLOP_BYPASS (1 << 11)
-#define PAD_FLOP_ENABLE (0 << 11)
+#define GP_FAMILY_RCOMP_CTRL(community, family) \
+(COMMUNITY_BASE(community) + 0x1080 + 0x80 * family)
-/* config0[10:9] - Pull str */
-#define PAD_PU_2K (0 << 9)
-#define PAD_PU_10K (1 << 9)
-#define PAD_PU_20K (2 << 9)
-#define PAD_PU_40K (3 << 9)
+#define GP_FAMILY_RCOMP_OFFSET(community, family) \
+(COMMUNITY_BASE(community) + 0x1084 + 0x80 * family)
-/* config0[8:7] - Pull assign */
-#define PAD_PULL_DISABLE (0 << 7)
-#define PAD_PULL_UP (1 << 7)
-#define PAD_PULL_DOWN (2 << 7)
+#define GP_FAMILY_RCOMP_OVERRIDE(community, family) \
+(COMMUNITY_BASE(community) + 0x1088 + 0x80 * family)
-/* config0[2:0] - Func. pin mux */
-#define PAD_FUNC0 0x0
-#define PAD_FUNC1 0x1
-#define PAD_FUNC2 0x2
-#define PAD_FUNC3 0x3
-#define PAD_FUNC4 0x4
-#define PAD_FUNC5 0x5
-#define PAD_FUNC6 0x6
+#define GP_FAMILY_RCOMP_VALUE(community, family) \
+(COMMUNITY_BASE(community) + 0x108C + 0x80 * family)
-/* pad config0 power-on values - We will not often want to change these */
-#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \
- PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \
- PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS)
+#define GP_FAMILY_CONF_COMP(community, family) \
+(COMMUNITY_BASE(community) + 0x1090 + 0x80 * family)
-/* pad config1 reg power-on values - Shouldn't need to change this */
-#define PAD_CONFIG1_DEFAULT 0x8000
+#define GP_FAMILY_CONF_REG(community, family) \
+(COMMUNITY_BASE(community) + 0x1094 + 0x80 * family)
-/* pad_val[2] - Iinenb - active low */
-#define PAD_VAL_INPUT_DISABLE (1 << 2)
-#define PAD_VAL_INPUT_ENABLE (0 << 2)
-/* pad_val[1] - Ioutenb - active low */
-#define PAD_VAL_OUTPUT_DISABLE (1 << 1)
-#define PAD_VAL_OUTPUT_ENABLE (0 << 1)
+/* Value written into pad control reg 0 */
+#define PAD_CONTROL_REG0_TRISTATE (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z)
-/* Input / Output state should usually be mutually exclusive */
-#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE)
-#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE)
+/* Calculate the MMIO Address for specific GPIO pin
+ * control register pointed by index.
+ */
+#define FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO)
+#define INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO)
+#define GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \
+ + (FAMILY_PAD_REGS_SIZE * FAMILY_NUMBER(gpio_pad) \
+ + (GPIO_REGS_SIZE * INTERNAL_PAD_NUM(gpio_pad))))
+
+/* Gpio to Pad mapping */
+#define SDMMC1_CMD_MMIO_OFFSET GPIO_OFFSET(23)
+#define SDMMC1_D0_MMIO_OFFSET GPIO_OFFSET(17)
+#define SDMMC1_D1_MMIO_OFFSET GPIO_OFFSET(24)
+#define SDMMC1_D2_MMIO_OFFSET GPIO_OFFSET(20)
+#define SDMMC1_D3_MMIO_OFFSET GPIO_OFFSET(26)
+#define MMC1_D4_SD_WE_MMIO_OFFSET GPIO_OFFSET(67)
+#define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65)
+#define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63)
+#define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68)
+#define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62)
+#define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67)
+
+/* GPIO Security registers offset */
+#define GPIO_READ_ACCESS_POLICY_REG 0x0000
+#define GPIO_WRITE_ACCESS_POLICY_REG 0x0100
+#define GPIO_WAKE_STATUS_REG 0x0200
+#define GPIO_WAKE_MASK_REG0 0x0280
+#define GPIO_WAKE_MASK_REG1 0x0284
+#define GPIO_INTERRUPT_STATUS 0x0300
+#define GPIO_INTERRUPT_MASK 0x0380
+#define GPE0A_STS_REG 0x20
+#define GPE0A_EN_REG 0x28
+#define ALT_GPIO_SMI_REG 0x38
+#define GPIO_ROUT_REG 0x58
-/* pad_val[0] - Value */
-#define PAD_VAL_HIGH (1 << 0)
-#define PAD_VAL_LOW (0 << 0)
+/* Pad register offset */
+#define PAD_CONF0_REG 0x0
+#define PAD_CONF1_REG 0x4
+#define PAD_VAL_REG 0x8
-/* pad_val reg power-on default varies by pad, and apparently can cause issues
- * if not set correctly, even if the pin isn't configured as GPIO. */
-#define PAD_VAL_DEFAULT PAD_VAL_INPUT
+/* Some banks have no legacy GPIO interface */
+#define GP_LEGACY_BASE_NONE 0xFFFF
-/* Configure GPIOs as MMIO by default */
-#define GPIO_INPUT_PU_10K \
- { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_MMIO, \
- .is_gpio = 1 }
+/* Number of GPIOs in each bank */
+#define GPNCORE_COUNT 27
+#define GPSCORE_COUNT 102
+#define GPSSUS_COUNT 44
+
+#define GP_SOUTHWEST_COUNT 56
+#define GP_NORTH_COUNT 59
+#define GP_EAST_COUNT 24
+#define GP_SOUTHEAST_COUNT 55
+
+/* General */
+#define GPIO_REGS_SIZE 8
+#define NA 0
+#define LOW 0
+#define HIGH 1
+#define MASK_WAKE 0
+#define UNMASK_WAKE 1
+#define GPE_CAPABLE 1
+#define GPE_CAPABLE_NONE 0
+
+#define MAX_FAMILY_PAD_GPIO_NO 15
+#define FAMILY_PAD_REGS_OFF 0x4400
+#define FAMILY_PAD_REGS_SIZE 0x400
+
+/* config0[31:28] - Interrupt Selection Interrupt Select */
+#define PAD_INT_SEL(int_s) (int_s << 28)
+
+/* config0[27:26] - Glitch Filter Config */
+#define PAD_GFCFG(glitch_cfg) (glitch_cfg << 26)
+#define PAD_GFCFG_DISABLE (0 << 26)
+#define PAD_ENABLE_EDGE_DETECTION (1 << 26) /* EDGE DETECTION ONLY */
+#define PAD_ENABLE_RX_DETECTION (2 << 26) /* RX DETECTION ONLY */
+#define PAD_ENABLE_EDGE_RX_DETECTION (3 << 26) /* RX & EDGE DETECTION */
+
+/* config0[25:24] - RX/TX Enable Config */
+#define PAD_FUNC_CTRL(tx_rx_enable) (tx_rx_enable << 24)
+#define PAD_FUNC_CTRL_RX_TX_ENABLE (0 << 24)
+#define PAD_FUNC_CTRL_TX_ENABLE_RX_DISABLE (1 << 24)
+#define PAD_FUNC_CTRL_TX_ENABLE_RX_ENABLE (2 << 24)
+#define PAD_TX_RX_ENABLE (3 << 24)
+
+/* config0[23:20] - Termination */
+#define PAD_PULL(TERM) (TERM << 20)
+#define PAD_PULL_DISABLE (0 << 20)
+#define PAD_PULL_DOWN_20K (1 << 20)
+#define PAD_PULL_DOWN_5K (2 << 20)
+#define PAD_PULL_DOWN_1K (4 << 20)
+#define PAD_PULL_UP_20K (9 << 20)
+#define PAD_PULL_UP_5K (10 << 20)
+#define PAD_PULL_UP_1K (12 << 20)
+
+/* config0[19:16] - PAD Mode */
+#define PAD_MODE_SELECTION(MODE_SEL) (MODE_SEL<<16)
+
+#define SET_PAD_MODE_SELECTION(pad_config, mode) \
+ ((pad_config & 0xfff0ffff) | PAD_MODE_SELECTION(mode))
+
+/* config0[15] - GPIO Enable */
+#define PAD_GPIO_DISABLE (0 << 15)
+#define PAD_GPIO_ENABLE (1 << 15)
+
+/* config0[14:11] - Reserver2 */
+
+/* config0[10:8] - GPIO Config */
+#define PAD_GPIO_CFG(gpio_cfg) (gpio_cfg << 8)
+#define PAD_GPIOFG_GPIO (0 << 8)
+#define PAD_GPIOFG_GPO (1 << 8)
+#define PAD_GPIOFG_GPI (2 << 8)
+#define PAD_GPIOFG_HI_Z (3 << 8)
+
+/* config0[7] - Gpio Light Mode Bar */
+/* config0[6:2] - Reserved1 */
+/* config0[1] - GPIO TX State */
+#define PAD_DEFAULT_TX(STATE) (STATE<<1)
+/* config0[0] - GPIO RX State */
+#define PAD_RX_BIT 1
+
+/* Pad Control Register 1 configuration */
+#define PAD_DISABLE_INT (0 << 0)
+#define PAD_TRIG_EDGE_LOW (1 << 0)
+#define PAD_TRIG_EDGE_HIGH (2 << 0)
+#define PAD_TRIG_EDGE_BOTH (3 << 0)
+#define PAD_TRIG_EDGE_LEVEL (4 << 0)
+
+/* Pad config0 power-on values */
+#define PAD_CONFIG0_DEFAULT 0x00010300
+#define PAD_CONFIG0_DEFAULT0 0x00910300
+#define PAD_CONFIG0_DEFAULT1 0x00110300
+#define PAD_CONFIG0_GPI_DEFAULT 0x00010200
+
+/* Pad config1 reg power-on values */
+#define PAD_CONFIG1_DEFAULT0 0x05C00000
+#define PAD_CONFIG1_CSEN 0x0DC00000
+#define PAD_CONFIG1_DEFAULT1 0x05C00020
+
+#define GPIO_INPUT_NO_PULL \
+ { .pad_conf0 = PAD_PULL_DISABLE | PAD_GPIO_ENABLE \
+ | PAD_CONFIG0_GPI_DEFAULT, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
#define GPIO_INPUT_PU_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_MMIO, \
- .is_gpio = 1 }
-
-#define GPIO_INPUT_PD_10K \
- { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_MMIO, \
- .is_gpio = 1 }
-
-#define GPIO_INPUT_PD_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_MMIO, \
- .is_gpio = 1 }
-
-#define GPIO_INPUT_NOPU \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_MMIO, \
- .is_gpio = 1 }
-
-#define GPIO_INPUT_LEGACY_NOPU \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_LEGACY, \
- .io_sel = GPIO_DIR_INPUT, \
- .is_gpio = 1 }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ_LEVELHIGH_NO_PULL \
- { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ_LEVELLOW_PU_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ_EDGELOW_PU_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ_EDGEHIGH_PD_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ_EDGELOW_PD_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-/* Direct / dedicated IRQ input - pass signal directly to apic */
-#define GPIO_DIRQ_EDGEBOTH_PU_20K \
- { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
- | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, }
-
-#define GPIO_OUT_LOW \
- { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \
- .use_sel = GPIO_USE_LEGACY, \
- .io_sel = GPIO_DIR_OUTPUT, \
- .gp_lvl = GPIO_LEVEL_LOW, \
- .is_gpio = 1 }
-
-#define GPIO_OUT_HIGH \
- { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \
- .use_sel = GPIO_USE_LEGACY, \
- .io_sel = GPIO_DIR_OUTPUT, \
- .gp_lvl = GPIO_LEVEL_HIGH, \
- .is_gpio = 1 }
-
-/* Define no-pull / PU / PD configs for each functional config option */
-#define GPIO_FUNC(_func, _pudir, _str) \
- { .use_sel = GPIO_USE_MMIO, \
- .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \
- PAD_CONFIG0_DEFAULT, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_DEFAULT }
-
-/* Default functional configs -- no PU */
-#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K)
-#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K)
-#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K)
-#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K)
-#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K)
-#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K)
-#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K)
-
-/* ACPI GPIO routing. Assume everything is externally pulled and negative edge
- * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */
-#define GPIO_ACPI_SCI \
- { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_LEGACY, \
- .io_sel = GPIO_DIR_INPUT, \
- .tne = 1, \
- .sci = 1, \
- .wake_en = 1, }
-#define GPIO_ACPI_WAKE \
- { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_LEGACY, \
- .io_sel = GPIO_DIR_INPUT, \
- .tne = 1, \
- .wake_en = 1, }
-#define GPIO_ACPI_SMI \
- { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
- .pad_conf1 = PAD_CONFIG1_DEFAULT, \
- .pad_val = PAD_VAL_INPUT, \
- .use_sel = GPIO_USE_LEGACY, \
- .io_sel = GPIO_DIR_INPUT, \
- .tne = 1, \
- .smi = 1}
+ { .pad_conf0 = PAD_PULL_UP_20K | PAD_GPIO_ENABLE \
+ | PAD_CONFIG0_GPI_DEFAULT, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
+#define GPIO_INPUT_PU_5K \
+ { .pad_conf0 = PAD_PULL_UP_5K | PAD_GPIO_ENABLE \
+ | PAD_CONFIG0_GPI_DEFAULT, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
+#define GPI(int_type, int_sel, term, int_msk, glitch_cfg, wake_msk, gpe_val) { \
+ .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GFCFG(glitch_cfg) \
+ | PAD_PULL(term) | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI, \
+ .pad_conf1 = int_type << 0 | PAD_CONFIG1_DEFAULT0, \
+ .wake_mask = wake_msk, \
+ .int_mask = int_msk, \
+ .gpe = gpe_val }
+
+#define GPO_FUNC(term, tx_state) {\
+ .pad_conf0 = PAD_GPIO_ENABLE | PAD_GPIOFG_GPO | PAD_PULL(term) \
+ | tx_state << 1, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
+#define NATIVE_FUNC(mode, term, inv_rx_tx) {\
+ .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \
+ | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 }
+
+#define NATIVE_FUNC_TX_RX(tx_rx_enable, mode, term, inv_rx_tx) {\
+ .pad_conf0 = PAD_FUNC_CTRL(tx_rx_enable) | PAD_GPIO_DISABLE \
+ | PAD_GPIOFG_GPIO | PAD_MODE_SELECTION(mode) \
+ | PAD_PULL(term),\
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 }
+
+#define NATIVE_FUNC_CSEN(mode, term, inv_rx_tx) {\
+ .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \
+ | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\
+ .pad_conf1 = PAD_CONFIG1_CSEN | inv_rx_tx << 4 }
+
+#define NATIVE_INT(mode, int_sel) {\
+ .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \
+ | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
+#define SPEAKER \
+{ .pad_conf0 = PAD_CONFIG0_DEFAULT0, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
+#define SPARE_PIN\
+ { .pad_conf0 = 0x00110300,\
+ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }
+
+/* SCI , SMI, Wake */
+#define GPIO_SCI(int_sel) \
+ { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\
+ | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
+ | PAD_INT_SEL(int_sel), \
+ .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
+ .gpe = SCI, \
+ .int_mask = 1 }
+
+#define GPIO_WAKE(int_sel) \
+ { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\
+ | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
+ | PAD_INT_SEL(int_sel), \
+ .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
+ .int_mask = 1 ,\
+ .wake_mask = 1 }
+
+#define GPIO_SMI(int_sel) \
+ { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\
+ | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \
+ | PAD_INT_SEL(int_sel), \
+ .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \
+ .int_mask = 1,\
+ .gpe = SMI }
+
+#define GPIO_SKIP { .skip_config = 1 }
+
+/* Common GPIO settings */
+#define NATIVE_DEFAULT(mode) NATIVE_FUNC(mode, 0, 0) /* no pull */
+#define NATIVE_PU20K(mode) NATIVE_FUNC(mode, 9, 0) /* PH 20k */
+#define NATIVE_PU5K(mode) NATIVE_FUNC(mode, 10, 0) /* PH 5k */
+#define NATIVE_PU5K_INVTX(mode) NATIVE_FUNC(mode, 10, inv_tx_enable) /* PH 5k */
+#define NATIVE_PU1K(mode) NATIVE_FUNC(mode, 12, 0) /* PH 1k */
+#define NATIVE_PU1K_CSEN_INVTX(mode) \
+ NATIVE_FUNC_CSEN(mode, 12, inv_tx_enable) /* PH 1k */
+#define NATIVE_PU1K_INVTX(mode) NATIVE_FUNC(mode, 12, inv_tx_enable) /* PH 1k */
+#define NATIVE_PD20K(mode) NATIVE_FUNC(mode, 1, 0) /* PD 20k */
+#define NATIVE_PD5K(mode) NATIVE_FUNC(mode, 2, 0) /* PD 5k */
+#define NATIVE_PD1K(mode) NATIVE_FUNC(mode, 4, 0) /* PD 1k */
+#define NATIVE_PD1K_CSEN_INVTX(mode) NATIVE_FUNC_CSEN(mode, 4, inv_tx_enable)
+ /* no pull */
+#define NATIVE_TX_RX_EN NATIVE_FUNC_TX_RX(3, 1, 0, inv_tx_enable)
+#define NATIVE_TX_RX_M1 NATIVE_FUNC_TX_RX(0, 1, 0, 0) /* no pull */
+#define NATIVE_TX_RX_M3 NATIVE_FUNC_TX_RX(0, 3, 0, 0) /* no pull */
+#define NATIVE_PU1K_M1 NATIVE_PU1K(1) /* PU1k M1 */
+
+/* Default native functions */
+#define Native_M0 NATIVE_DEFAULT(0)
+#define Native_M1 NATIVE_DEFAULT(1)
+#define Native_M2 NATIVE_DEFAULT(2)
+#define Native_M3 NATIVE_DEFAULT(3)
+#define Native_M4 NATIVE_DEFAULT(4)
+#define Native_M5 NATIVE_DEFAULT(5)
+#define Native_M6 NATIVE_DEFAULT(6)
+#define Native_M7 NATIVE_DEFAULT(7)
+#define Native_M8 NATIVE_DEFAULT(8)
+
+#define GPIO_OUT_LOW GPO_FUNC(0, 0) /* gpo low */
+#define GPIO_OUT_HIGH GPO_FUNC(0, 1) /* gpo high */
+#define GPIO_NC GPIO_INPUT_PU_20K /* not connect */
/* End marker */
#define GPIO_LIST_END 0xffffffff
@@ -317,143 +351,226 @@
#define GPIO_END \
{ .pad_conf0 = GPIO_LIST_END }
-/* Common default GPIO settings */
-#define GPIO_INPUT GPIO_INPUT_NOPU
-#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU
-#define GPIO_INPUT_PU GPIO_INPUT_PU_20K
-#define GPIO_INPUT_PD GPIO_INPUT_PD_20K
-#define GPIO_NC GPIO_OUT_HIGH
-#define GPIO_DEFAULT GPIO_FUNC0
-
/* 16 DirectIRQs per supported bank */
-#define GPIO_MAX_DIRQS 16
-
-/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO
- * function 1. Indicate first / last GPIOs with function 1. */
-#define GPIO_NONE 255
-/* All NCORE GPIOs are function 0 */
-#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE
-#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE
-/* SCORE GPIO [92:93] are function 1 */
-#define GPSCORE_GPIO_F1_RANGE_START 92
-#define GPSCORE_GPIO_F1_RANGE_END 93
-/* SSUS GPIO [11:21] are function 1 */
-#define GPSSUS_GPIO_F1_RANGE_START 11
-#define GPSSUS_GPIO_F1_RANGE_END 21
+#define GPIO_MAX_DIRQS 16
+
+#define GPIO_NONE 255
+
+/* Functions / defines for changing GPIOs in romstage */
+/* SCORE Pad definitions. */
+#define UART_RXD_PAD 82
+#define UART_TXD_PAD 83
+#define PCU_SMB_CLK_PAD 88
+#define PCU_SMB_DATA_PAD 90
+#define SOC_DDI1_VDDEN_PAD 16
+#define UART1_RXD_PAD 9
+#define UART1_TXD_PAD 13
+#define DDI2_DDC_SCL 48
+#define DDI2_DDC_SDA 53
struct soc_gpio_map {
u32 pad_conf0;
u32 pad_conf1;
u32 pad_val;
- u32 use_sel : 1;
- u32 io_sel : 1;
- u32 gp_lvl : 1;
- u32 tpe : 1;
- u32 tne : 1;
- u32 wake_en : 1;
- u32 smi : 1;
- u32 is_gpio : 1;
- u32 sci : 1;
+ u32 gpe;
+ u32 int_mask:1;
+ u32 wake_mask:1;
+ u32 is_gpio:1;
+ u32 skip_config:1;
} __attribute__ ((packed));
struct soc_gpio_config {
- const struct soc_gpio_map *ncore;
- const struct soc_gpio_map *score;
- const struct soc_gpio_map *ssus;
- const u8 (*core_dirq)[GPIO_MAX_DIRQS];
- const u8 (*sus_dirq)[GPIO_MAX_DIRQS];
+ const struct soc_gpio_map *north;
+ const struct soc_gpio_map *southeast;
+ const struct soc_gpio_map *southwest;
+ const struct soc_gpio_map *east;
};
-/* Description of GPIO 'bank' ex. {ncore, score. ssus} */
+/* Description of a GPIO 'community' */
struct gpio_bank {
const int gpio_count;
- const u8* gpio_to_pad;
+ const u8 *gpio_to_pad;
const int legacy_base;
const unsigned long pad_base;
- const u8 has_wake_en :1;
- const u8 gpio_f1_range_start;
- const u8 gpio_f1_range_end;
+ const u8 has_gpe_en:1;
+ const u8 has_wake_en:1;
};
-void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap);
-/* This function is weak and can be overridden by a mainboard function. */
-struct soc_gpio_config* mainboard_get_gpios(void);
+typedef enum {
+ NATIVE = 0xff,
+ GPIO = 0, /* Native, no need to set PAD_VALUE */
+ GPO = 1, /* GPI, input only in PAD_VALUE */
+ GPI = 2, /* GPO, output only in PAD_VALUE */
+ HI_Z = 3,
+ NA_GPO = 0,
+} gpio_en_t;
+
+typedef enum {
+ LO = 0,
+ HI = 1,
+} gpo_d4_t;
+
+typedef enum {
+ F0 = 0,
+ F1 = 1,
+ F2 = 2,
+ F3 = 3
+} gpio_func_num_t;
+
+typedef enum {
+ _CAP = 1,
+ _NOT_CAP = 0
+} int_capable_t;
+
+typedef enum {
+ P_NONE = 0, /* Pull None */
+ P_20K_L = 1, /* Pull Down 20K */
+ P_5K_L = 2, /* Pull Down 5K */
+ P_1K_L = 4, /* Pull Down 1K */
+ P_20K_H = 9, /* Pull Up 20K */
+ P_5K_H = 10, /* Pull Up 5K */
+ P_1K_H = 12 /* Pull Up 1K */
+} pull_type_t;
+
+typedef enum {
+ DISABLE = 0, /* Disable */
+ ENABLE = 1, /* Enable */
+} park_mode_enb_t;
+
+typedef enum {
+ VOLT_3_3 = 0, /* Working on 3.3 Volts */
+ VOLT_1_8 = 1, /* Working on 1.8 Volts */
+} voltage_t;
+
+typedef enum {
+ DISABLE_HS = 0, /* Disable high speed mode */
+ ENABLE_HS = 1, /* Enable high speed mode */
+} hs_mode_t;
+
+typedef enum {
+ PULL_UP = 0, /* On Die Termination Up */
+ PULL_DOWN = 1, /* On Die Termination Down */
+} odt_up_dn_t;
+
+typedef enum {
+ DISABLE_OD = 0, /* On Die Termination Disable */
+ ENABLE_OD = 1, /* On Die Termination Enable */
+} odt_en_t;
+
+typedef enum {
+ ONE_BIT = 1,
+ TWO_BIT = 3,
+ THREE_BIT = 7,
+ FOUR_BIT = 15,
+ FIVE_BIT = 31,
+ SIX_BIT = 63,
+ SEVEN_BIT = 127,
+ EIGHT_BIT = 255
+} bit_t;
+
+typedef enum {
+ M0 = 0,
+ M1,
+ M2,
+ M3,
+ M4,
+ M5,
+ M6,
+ M7,
+ M8,
+ M9,
+ M10,
+ M11,
+ M12,
+ M13,
+} mode_list_t;
+
+typedef enum {
+ L0 = 0,
+ L1 = 1,
+ L2 = 2,
+ L3 = 3,
+ L4 = 4,
+ L5 = 5,
+ L6 = 6,
+ L7 = 7,
+ L8 = 8,
+ L9 = 9,
+ L10 = 10,
+ L11 = 11,
+ L12 = 12,
+ L13 = 13,
+ L14 = 14,
+ L15 = 15,
+} int_select_t;
+
+typedef enum {
+ INT_DIS = 0,
+ trig_edge_low = 1,
+ trig_edge_high = 2,
+ trig_edge_both = 3,
+ trig_level = 4,
+} int_type_t;
+
+typedef enum {
+ glitch_disable = 0,
+ en_edge_detect,
+ en_rx_data,
+ en_edge_rx_data,
+} glitch_cfg;
+
+typedef enum {
+ maskable = 0,
+ non_maskable,
+} mask_t;
+
+typedef enum {
+ GPE = 0,
+ SMI,
+ SCI,
+} gpe_config_t;
-/* Functions / defines for changing GPIOs in romstage */
-/* SCORE Pad definitions. */
-#define UART_RXD_PAD 82
-#define UART_TXD_PAD 83
-#define PCU_SMB_CLK_PAD 88
-#define PCU_SMB_DATA_PAD 90
-#define SOC_DDI1_VDDEN_PAD 16
-
-static inline u32 *ncore_pconf0(int pad_num)
-{
- return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16);
-}
-
-static inline void ncore_select_func(int pad, int func)
-{
- uint32_t reg;
- u32 *pconf0_addr = ncore_pconf0(pad);
-
- reg = read32(pconf0_addr);
- reg &= ~0x7;
- reg |= func & 0x7;
- write32(pconf0_addr, reg);
-}
-
-static inline u32 *score_pconf0(int pad_num)
-{
- return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16);
-}
-
-static inline u32 *ssus_pconf0(int pad_num)
-{
- return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16);
-}
+/*
+ * InvertRxTx 7:4
+ * 0 - No Inversion
+ * 1 - Inversion
+ * [0] RX Enable
+ * [1] TX Enable
+ * [2] RX Data
+ * [3] TX Data
+ */
+typedef enum {
+ no_inversion = 0,
+ inv_rx_enable = 0x1,
+ inv_tx_enable = 0x2,
+ inv_rx_tx_enable = 0x3,
+ inv_rx_data = 0x4,
+ inv_tx_data = 0x8,
+} invert_rx_tx_t;
-static inline void score_select_func(int pad, int func)
-{
- uint32_t reg;
- uint32_t *pconf0_addr = score_pconf0(pad);
+#define PAD_VAL_HIGH (1 << 0)
- reg = read32(pconf0_addr);
- reg &= ~0x7;
- reg |= func & 0x7;
- write32(pconf0_addr, reg);
-}
+void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap);
+struct soc_gpio_config *mainboard_get_gpios(void);
-static inline void ssus_select_func(int pad, int func)
+static inline void ncore_select_func(int pad, int func)
{
- uint32_t reg;
- uint32_t *pconf0_addr = ssus_pconf0(pad);
- reg = read32(pconf0_addr);
- reg &= ~0x7;
- reg |= func & 0x7;
- write32(pconf0_addr, reg);
}
/* These functions require that the input pad be configured as an input GPIO */
-static inline int score_get_gpio(int pad)
-{
- uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
-
- return read32(val_addr) & PAD_VAL_HIGH;
-}
static inline int ssus_get_gpio(int pad)
{
- uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
-
- return read32(val_addr) & PAD_VAL_HIGH;
+ return 0;
}
static inline void ssus_disable_internal_pull(int pad)
{
- const uint32_t pull_mask = ~(0xf << 7);
- write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
}
-#endif /* _BAYTRAIL_GPIO_H_ */
+int get_gpio(int community_base, int pad0_offset);
+uint16_t gpio_family_number(uint8_t community, uint8_t pad);
+uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad);
+
+#endif /* _SOC_GPIO_H_ */
diff --git a/src/soc/intel/braswell/include/soc/hda.h b/src/soc/intel/braswell/include/soc/hda.h
new file mode 100644
index 0000000..11fd404
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/hda.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _SOC_HDA_H_
+#define _SOC_HDA_H_
+
+/*
+ * PCI config registers.
+ */
+
+#define HDA_DCKSTS 0x4d
+# define HDA_DCKSTS_DS (1 << 7)
+# define HDA_DCKSTS_DM (1 << 0)
+
+#define HDA_DEVC 0x78
+# define HDA_DEVC_MRRS 0x7000
+# define HDA_DEVC_NSNPEN (1 << 11)
+# define HDA_DEVC_AUXPEN (1 << 10)
+# define HDA_DEVC_PEEN (1 << 9)
+# define HDA_DEVC_ETEN (1 << 8)
+# define HDA_DEVC_MAXPAY 0x00e0
+# define HDA_DEVC_ROEN (1 << 4)
+# define HDA_DEVC_URREN (1 << 3)
+# define HDA_DEVC_FEREN (1 << 2)
+# define HDA_DEVC_NFEREN (1 << 1)
+# define HDA_DEVC_CEREN (1 << 0)
+
+#endif /* _SOC_HDA_H_ */
diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h
index 5c5e9ab..c4775ea 100644
--- a/src/soc/intel/braswell/include/soc/iomap.h
+++ b/src/soc/intel/braswell/include/soc/iomap.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,8 +18,8 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_IOMAP_H_
-#define _BAYTRAIL_IOMAP_H_
+#ifndef _SOC_IOMAP_H_
+#define _SOC_IOMAP_H_
/*
@@ -38,11 +39,12 @@
#define PMC_BASE_SIZE 0x400
/* IO Memory */
-#define IO_BASE_ADDRESS 0xfed0c000
-#define IO_BASE_OFFSET_GPSCORE 0x0000
-#define IO_BASE_OFFSET_GPNCORE 0x1000
-#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_ADDRESS 0xfed80000
#define IO_BASE_SIZE 0x4000
+#define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000
+#define COMMUNITY_OFFSET_GPNORTH 0x08000
+#define COMMUNITY_OFFSET_GPEAST 0x10000
+#define COMMUNITY_OFFSET_GPSOUTHEAST 0x18000
/* Intel Legacy Block */
#define ILB_BASE_ADDRESS 0xfed08000
@@ -53,11 +55,11 @@
#define SPI_BASE_SIZE 0x400
/* MODPHY */
-#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_ADDRESS 0xfea00000
#define MPHY_BASE_SIZE 0x100000
/* Power Management Unit */
-#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_ADDRESS 0xfed06000
#define PUNIT_BASE_SIZE 0x800
/* Root Complex Base Address */
@@ -87,4 +89,4 @@
uint32_t nc_read_top_of_low_memory(void);
#endif
-#endif /* _BAYTRAIL_IOMAP_H_ */
+#endif /* _SOC_IOMAP_H_ */
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index bf67294..60763d9 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -2,13 +2,14 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
@@ -17,29 +18,33 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_IOSF_H_
-#define _BAYTRAIL_IOSF_H_
+#ifndef _SOC_IOSF_H_
+#define _SOC_IOSF_H_
#include <stdint.h>
+#if ENV_RAMSTAGE
+#include <device/device.h>
+#include <reg_script.h>
+#endif /* ENV_RAMSTAGE */
#include <soc/pci_devs.h>
/*
- * The Bay Trail SoC has a message network called IOSF Sideband. The access
+ * The SoC has a message network called IOSF Sideband. The access
* routines are through 3 registers in PCI config space of 00:00.0:
* MCR - control register
* MDR - data register
* MCRX - control register extension
- * The extension regist is only used for addresses that don't fit into the
- * 8 bit register address.
+ * The extension register is only used for addresses that don't fit
+ * into the 8 bit register address.
*/
#ifndef PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN) ( \
- (((SEGBUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x07) << 12))
+ (((SEGBUS) & 0xFFF) << 20) | \
+ (((DEV) & 0x1F) << 15) | \
+ (((FN) & 0x07) << 12))
#endif
-#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC)
+#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC)
#define MCR_REG 0xd0
#define IOSF_OPCODE(x) ((x) << 24)
@@ -55,63 +60,29 @@
#define MDR_REG 0xd4
#define MCRX_REG 0xd8
-uint32_t iosf_aunit_read(int reg);
-void iosf_aunit_write(int reg, uint32_t val);
-uint32_t iosf_cpu_bus_read(int reg);
-void iosf_cpu_bus_write(int reg, uint32_t val);
uint32_t iosf_bunit_read(int reg);
void iosf_bunit_write(int reg, uint32_t val);
-uint32_t iosf_dunit_read(int reg);
-void iosf_dunit_write(int reg, uint32_t val);
-/* Some registers are per channel while the globals live in dunit 0 */
-uint32_t iosf_dunit_ch0_read(int reg);
-uint32_t iosf_dunit_ch1_read(int reg);
uint32_t iosf_punit_read(int reg);
void iosf_punit_write(int reg, uint32_t val);
-uint32_t iosf_usbphy_read(int reg);
-void iosf_usbphy_write(int reg, uint32_t val);
-uint32_t iosf_ushphy_read(int reg);
-void iosf_ushphy_write(int reg, uint32_t val);
-uint32_t iosf_sec_read(int reg);
-void iosf_sec_write(int reg, uint32_t val);
-uint32_t iosf_port45_read(int reg);
-void iosf_port45_write(int reg, uint32_t val);
-uint32_t iosf_port46_read(int reg);
-void iosf_port46_write(int reg, uint32_t val);
-uint32_t iosf_port47_read(int reg);
-void iosf_port47_write(int reg, uint32_t val);
-uint32_t iosf_port55_read(int reg);
-void iosf_port55_write(int reg, uint32_t val);
-uint32_t iosf_port58_read(int reg);
-void iosf_port58_write(int reg, uint32_t val);
-uint32_t iosf_port59_read(int reg);
-void iosf_port59_write(int reg, uint32_t val);
-uint32_t iosf_port5a_read(int reg);
-void iosf_port5a_write(int reg, uint32_t val);
-uint32_t iosf_lpss_read(int reg);
-void iosf_lpss_write(int reg, uint32_t val);
-uint32_t iosf_ccu_read(int reg);
-void iosf_ccu_write(int reg, uint32_t val);
uint32_t iosf_score_read(int reg);
void iosf_score_write(int reg, uint32_t val);
+uint32_t iosf_lpss_read(int reg);
+void iosf_lpss_write(int reg, uint32_t val);
+uint32_t iosf_port58_read(int reg);
+void iosf_port58_write(int reg, uint32_t val);
uint32_t iosf_scc_read(int reg);
void iosf_scc_write(int reg, uint32_t val);
-uint32_t iosf_porta2_read(int reg);
-void iosf_porta2_write(int reg, uint32_t val);
-uint32_t iosf_ssus_read(int reg);
-void iosf_ssus_write(int reg, uint32_t val);
+
+#if ENV_RAMSTAGE
+uint64_t reg_script_read_iosf(struct reg_script_context *ctx);
+void reg_script_write_iosf(struct reg_script_context *ctx);
+#endif /* ENV_RAMSTAGE */
/* IOSF ports. */
#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */
-#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */
-#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */
#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */
#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */
#define IOSF_PORT_PMC 0x04 /* Power Management Controller */
-#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */
-#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */
-#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */
-#define IOSF_PORT_USBPHY 0x43 /* USB PHY */
#define IOSF_PORT_SEC 0x44 /* SEC */
#define IOSF_PORT_0x45 0x45
#define IOSF_PORT_0x46 0x46
@@ -125,148 +96,42 @@ void iosf_ssus_write(int reg, uint32_t val);
#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */
#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */
#define IOSF_PORT_0xa2 0xa2
-#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */
-#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */
#define IOSF_PORT_SSUS 0xa8 /* SUS */
#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */
/* Read and write opcodes differ per port. */
-#define IOSF_OP_READ_AUNIT 0x10
-#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1)
-#define IOSF_OP_READ_SYSMEMC 0x10
-#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1)
-#define IOSF_OP_READ_CPU_BUS 0x10
-#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1)
#define IOSF_OP_READ_BUNIT 0x10
#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1)
#define IOSF_OP_READ_PMC 0x06
#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1)
-#define IOSF_OP_READ_GFX 0x00
-#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1)
-#define IOSF_OP_READ_SYSMEMIO 0x06
-#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1)
-#define IOSF_OP_READ_USBPHY 0x06
-#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1)
-#define IOSF_OP_READ_SEC 0x04
-#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1)
-#define IOSF_OP_READ_0x45 0x06
-#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1)
-#define IOSF_OP_READ_0x46 0x06
-#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1)
-#define IOSF_OP_READ_0x47 0x06
-#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1)
#define IOSF_OP_READ_SCORE 0x06
#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1)
-#define IOSF_OP_READ_0x55 0x04
-#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1)
-#define IOSF_OP_READ_0x58 0x06
-#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1)
-#define IOSF_OP_READ_0x59 0x06
-#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1)
-#define IOSF_OP_READ_0x5a 0x04
-#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1)
-#define IOSF_OP_READ_USHPHY 0x06
-#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1)
-#define IOSF_OP_READ_SCC 0x06
-#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1)
#define IOSF_OP_READ_LPSS 0x06
#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1)
-#define IOSF_OP_READ_0xa2 0x06
-#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1)
-#define IOSF_OP_READ_SATAPHY 0x00
-#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1)
-#define IOSF_OP_READ_PCIEPHY 0x00
-#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1)
-#define IOSF_OP_READ_SSUS 0x10
-#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1)
-#define IOSF_OP_READ_CCU 0x06
-#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1)
+#define IOSF_OP_READ_0x58 0x06
+#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1)
+#define IOSF_OP_READ_SCC 0x06
+#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1)
/*
* BUNIT Registers.
*/
-#define BNOCACHE 0x23
/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */
#define BUNIT_BMBOUND 0x25
-/* BMBOUND_HI describes the available ram above 4GiB. It has a
+/*
+ * BMBOUND_HI describes the available ram above 4GiB. It has a
* 256MiB granularity. Physical address bits 35:28 are compared with 31:24
* bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB
* granularity care needs to be taken with the e820 map to account for a hole
- * in the ram. */
+ * in the ram.
+ */
#define BUNIT_BMBOUND_HI 0x26
#define BUNIT_MMCONF_REG 0x27
+#define BUNIT_BMISC 0x28
/* The SMMRR registers define the SMM region in MiB granularity. */
-#define BUNIT_SMRCP 0x2b
-#define BUNIT_SMRRAC 0x2c
-#define BUNIT_SMRWAC 0x2d
#define BUNIT_SMRRL 0x2e
#define BUNIT_SMRRH 0x2f
-# define BUNIT_SMRR_ENABLE (1 << 31)
-
-/* SA ID bits. */
-#define SAI_IA_UNTRUSTED (1 << 0)
-#define SAI_IA_SMM (1 << 2)
-#define SAI_IA_BOOT (1 << 4)
-
-/*
- * DUNIT Registers.
- */
-
-#define DRP 0x00
-# define DRP_DIMM0_RANK0_EN (0x01 << 0)
-# define DRP_DIMM0_RANK1_EN (0x01 << 1)
-# define DRP_DIMM1_RANK0_EN (0x01 << 2)
-# define DRP_DIMM1_RANK1_EN (0x01 << 3)
-# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \
- DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN)
-#define DTR0 0x01
-# define DTR0_SPEED_MASK 0x03
-# define DTR0_SPEED_800 0x00
-# define DTR0_SPEED_1066 0x01
-# define DTR0_SPEED_1333 0x02
-# define DTR0_SPEED_1600 0x03
-
-/*
- * PUNIT Registers
- */
-#define SB_BIOS_CONFIG 0x06
-# define SB_BIOS_CONFIG_ECC_EN (1 << 31)
-# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30)
-# define SB_BIOS_CONFIG_EFF_ECC (1 << 29)
-# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28)
-# define SB_BIOS_CONFIG_PERF_MODE (1 << 17)
-# define SB_BIOS_CONFIG_PDM_MODE (1 << 16)
-# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8)
-# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7)
-# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3)
-# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2)
-# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1)
-# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0)
-#define BIOS_RESET_CPL 0x05
-# define BIOS_RESET_CPL_ALL_DONE (1 << 1)
-# define BIOS_RESET_CPL_RESET_DONE (1 << 0)
-#define PUNIT_PWRGT_CONTROL 0x60
-#define PUNIT_PWRGT_STATUS 0x61
-#define PUNIT_GPU_EC_VIRUS 0xd2
-
-#define PUNIT_SOC_POWER_BUDGET 0x02
-#define PUNIT_SOC_ENERGY_CREDIT 0x03
-#define PUNIT_PTMC 0x80
-#define PUNIT_GFXT 0x88
-#define PUNIT_VEDT 0x89
-#define PUNIT_ISPT 0x8c
-#define PUNIT_PTPS 0xb2
-#define PUNIT_TE_AUX0 0xb5
-#define PUNIT_TE_AUX1 0xb6
-#define PUNIT_TE_AUX2 0xb7
-#define PUNIT_TE_AUX3 0xb8
-#define PUNIT_TTE_VRIccMax 0xb9
-#define PUNIT_TTE_VRHot 0xba
-#define PUNIT_TTE_XXPROCHOT 0xbb
-#define PUNIT_TTE_SLM0 0xbc
-#define PUNIT_TTE_SLM1 0xbd
-#define PUNIT_TTE_SWT 0xbf
/*
* LPSS Registers
@@ -296,54 +161,37 @@ void iosf_ssus_write(int reg, uint32_t val);
*/
#define SCC_SD_CTL 0x504
#define SCC_SDIO_CTL 0x508
-#define SCC_MMC_CTL 0x50c
+#define SCC_MMC_CTL 0x500
# define SCC_CTL_PCI_CFG_DIS (1 << 0)
# define SCC_CTL_ACPI_INT_EN (1 << 1)
/*
- * CCU Registers
- */
-
-#define PLT_CLK_CTRL_0 0x3c
-#define PLT_CLK_CTRL_1 0x40
-#define PLT_CLK_CTRL_2 0x44
-#define PLT_CLK_CTRL_3 0x48
-#define PLT_CLK_CTRL_4 0x4c
-#define PLT_CLK_CTRL_5 0x50
-# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1)
-# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1)
-# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0)
-
-/*
- * USBPHY Registers
- */
-#define USBPHY_COMPBG 0x7f04
-#define USBPHY_PER_PORT_LANE0 0x4100
-#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122
-#define USBPHY_PER_PORT_LANE1 0x4200
-#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222
-#define USBPHY_PER_PORT_LANE2 0x4300
-#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322
-#define USBPHY_PER_PORT_LANE3 0x4400
-#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422
-
-/*
- * USHPHY Registers
- */
-#define USHPHY_CDN_PLL_CONTROL 0x03c0
-#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054
-#define USHPHY_CCDRLF 0x8040
-#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8
-#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0
-#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080
-#define USHPHY_REE_DAC_CONTROL 0x80b8
-#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000
-
-/*
* LPE Registers
*/
#define LPE_PCICFGCTR1 0x0500
# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0)
# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1)
-#endif /* _BAYTRAIL_IOSF_H_ */
+/*
+ * IO Sideband Function
+ */
+
+#if ENV_RAMSTAGE
+#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
+ _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \
+ REG_SCRIPT_TYPE_IOSF, \
+ REG_SCRIPT_SIZE_32, \
+ reg_, mask_, value_, timeout_, unit_)
+#define REG_IOSF_READ(unit_, reg_) \
+ REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
+#define REG_IOSF_WRITE(unit_, reg_, value_) \
+ REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
+#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
+ REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
+#define REG_IOSF_OR(unit_, reg_, value_) \
+ REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
+#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
+ REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
+#endif /* ENV_RAMSTAGE */
+
+#endif /* _SOC_IOSF_H_ */
diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h
index 4f9f059..3367873 100644
--- a/src/soc/intel/braswell/include/soc/irq.h
+++ b/src/soc/intel/braswell/include/soc/irq.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,8 +18,8 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_IRQ_H_
-#define _BAYTRAIL_IRQ_H_
+#ifndef _SOC_IRQ_H_
+#define _SOC_IRQ_H_
#define PIRQA_APIC_IRQ 16
#define PIRQB_APIC_IRQ 17
@@ -28,6 +29,7 @@
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
+
/* The below IRQs are for when devices are in ACPI mode. Active low. */
#define LPE_DMA0_IRQ 24
#define LPE_DMA1_IRQ 25
@@ -47,50 +49,101 @@
#define LPSS_SPI_IRQ 41
#define LPSS_DMA1_IRQ 42
#define LPSS_DMA2_IRQ 43
-#define SCC_EMMC_IRQ 44
+#define SCC_EMMC_IRQ 45
#define SCC_SDIO_IRQ 46
-#define SCC_SD_IRQ 47
-#define GPIO_NC_IRQ 48
-#define GPIO_SC_IRQ 49
-#define GPIO_SUS_IRQ 50
+#define SCC_SD_IRQ 47
+
+#define GPIO_N_IRQ 48
+#define GPIO_SW_IRQ 49
+#define GPIO_E_IRQ 50
+
/* GPIO direct / dedicated IRQs. */
-#define GPIO_S0_DED_IRQ_0 51
-#define GPIO_S0_DED_IRQ_1 52
-#define GPIO_S0_DED_IRQ_2 53
-#define GPIO_S0_DED_IRQ_3 54
-#define GPIO_S0_DED_IRQ_4 55
-#define GPIO_S0_DED_IRQ_5 56
-#define GPIO_S0_DED_IRQ_6 57
-#define GPIO_S0_DED_IRQ_7 58
-#define GPIO_S0_DED_IRQ_8 59
-#define GPIO_S0_DED_IRQ_9 60
-#define GPIO_S0_DED_IRQ_10 61
-#define GPIO_S0_DED_IRQ_11 62
-#define GPIO_S0_DED_IRQ_12 63
-#define GPIO_S0_DED_IRQ_13 64
-#define GPIO_S0_DED_IRQ_14 65
-#define GPIO_S0_DED_IRQ_15 66
-#define GPIO_S5_DED_IRQ_0 67
-#define GPIO_S5_DED_IRQ_1 68
-#define GPIO_S5_DED_IRQ_2 69
-#define GPIO_S5_DED_IRQ_3 70
-#define GPIO_S5_DED_IRQ_4 71
-#define GPIO_S5_DED_IRQ_5 72
-#define GPIO_S5_DED_IRQ_6 73
-#define GPIO_S5_DED_IRQ_7 74
-#define GPIO_S5_DED_IRQ_8 75
-#define GPIO_S5_DED_IRQ_9 76
-#define GPIO_S5_DED_IRQ_10 77
-#define GPIO_S5_DED_IRQ_11 78
-#define GPIO_S5_DED_IRQ_12 79
-#define GPIO_S5_DED_IRQ_13 80
-#define GPIO_S5_DED_IRQ_14 81
-#define GPIO_S5_DED_IRQ_15 82
+
+/* NORTH COMMUNITY */
+#define GPIO_N_DED_IRQ_0 51
+#define GPIO_N_DED_IRQ_1 52
+#define GPIO_N_DED_IRQ_2 53
+#define GPIO_N_DED_IRQ_3 54
+#define GPIO_N_DED_IRQ_4 55
+#define GPIO_N_DED_IRQ_5 56
+#define GPIO_N_DED_IRQ_6 57
+#define GPIO_N_DED_IRQ_7 58
+
+/* SOUTH WEST COMMUNITY */
+#define GPIO_SW_DED_IRQ_0 59
+#define GPIO_SW_DED_IRQ_1 60
+#define GPIO_SW_DED_IRQ_2 61
+#define GPIO_SW_DED_IRQ_3 62
+#define GPIO_SW_DED_IRQ_4 63
+#define GPIO_SW_DED_IRQ_5 64
+#define GPIO_SW_DED_IRQ_6 65
+#define GPIO_SW_DED_IRQ_7 66
+
+/* EAST COMMUNITY */
+#define GPIO_E_DED_IRQ_0 67
+#define GPIO_E_DED_IRQ_1 68
+#define GPIO_E_DED_IRQ_2 69
+#define GPIO_E_DED_IRQ_3 70
+#define GPIO_E_DED_IRQ_4 71
+#define GPIO_E_DED_IRQ_5 72
+#define GPIO_E_DED_IRQ_6 73
+#define GPIO_E_DED_IRQ_7 74
+#define GPIO_E_DED_IRQ_8 75
+#define GPIO_E_DED_IRQ_9 76
+#define GPIO_E_DED_IRQ_10 77
+#define GPIO_E_DED_IRQ_11 78
+#define GPIO_E_DED_IRQ_12 79
+#define GPIO_E_DED_IRQ_13 80
+#define GPIO_E_DED_IRQ_14 81
+#define GPIO_E_DED_IRQ_15 82
+
+/* More IRQ */
+#define LPSS_SPI2_IRQ 89
+#define LPSS_SPI3_IRQ 90
+#define GPIO_SE_IRQ 91
+
+/* GPIO direct / dedicated IRQs. */
+/* SOUTH EAST COMMUNITY */
+#define GPIO_SE_DED_IRQ_0 92
+#define GPIO_SE_DED_IRQ_1 93
+#define GPIO_SE_DED_IRQ_2 94
+#define GPIO_SE_DED_IRQ_3 95
+#define GPIO_SE_DED_IRQ_4 96
+#define GPIO_SE_DED_IRQ_5 97
+#define GPIO_SE_DED_IRQ_6 98
+#define GPIO_SE_DED_IRQ_7 99
+#define GPIO_SE_DED_IRQ_8 100
+#define GPIO_SE_DED_IRQ_9 101
+#define GPIO_SE_DED_IRQ_10 102
+#define GPIO_SE_DED_IRQ_11 103
+#define GPIO_SE_DED_IRQ_12 104
+#define GPIO_SE_DED_IRQ_13 105
+#define GPIO_SE_DED_IRQ_14 106
+#define GPIO_SE_DED_IRQ_15 107
+
+/* OTHER IRQs */
+#define GPIO_VIRTUAL 108
+#define LPE_DMA2 109
+#define LPE_SSP3 110
+#define LPE_SSP4 111
+#define LPE_SSP5 112
+
/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */
-#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
-#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
-#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
-#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
+#define _GPIO_N_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot
+#define _GPIO_SW_DED_IRQ(slot) GPIO_SW_DED_IRQ_##slot
+#define _GPIO_E_DED_IRQ(slot) GPIO_E_DED_IRQ_##slot
+#define _GPIO_SE_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot
+#define GPIO_N_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot)
+#define GPIO_SW_DED_IRQ(slot) _GPIO_SW_DED_IRQ(slot)
+#define GPIO_E_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot)
+#define GPIO_SE_DED_IRQ(slot) _GPIO_SE_DED_IRQ(slot)
+
+/* TODO NEED TO UPDATE THESE IN onboard.h */
+#define _GPIO_S0_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot)
+
/* PIC IRQ settings. */
#define PIRQ_PIC_IRQDISABLE 0x0
@@ -127,9 +180,11 @@
# define SCIS_IRQ22 0x06
# define SCIS_IRQ23 0x07
-/* In each mainboard directory there should exist a header file irqroute.h that
+/*
+ * In each mainbaord directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
- * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
+ * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries.
+ */
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#include <stdint.h>
@@ -137,28 +192,29 @@
#define NUM_IR_DEVS 32
#define NUM_PIRQS 8
-struct baytrail_irq_route {
+struct soc_irq_route {
/* Per device configuration. */
uint16_t pcidev[NUM_IR_DEVS];
/* Route path for each internal PIRQx in PIC mode. */
uint8_t pic[NUM_PIRQS];
};
-extern const struct baytrail_irq_route global_baytrail_irq_route;
+extern const struct soc_irq_route global_soc_irq_route;
#define DEFINE_IRQ_ROUTES \
- const struct baytrail_irq_route global_baytrail_irq_route = { \
+ const struct soc_irq_route global_soc_irq_route = { \
.pcidev = { PCI_DEV_PIRQ_ROUTES, }, \
.pic = { PIRQ_PIC_ROUTES, }, \
}
+/* The following macros are used for ACPI by the ASL compiler */
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
- [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
- ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)
+ [dev_] = (((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
+ ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0))
#define PIRQ_PIC(pirq_, pic_irq_) \
[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
-#endif /* _BAYTRAIL_IRQ_H_ */
+#endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h
index 7247080..032cf9a 100644
--- a/src/soc/intel/braswell/include/soc/lpc.h
+++ b/src/soc/intel/braswell/include/soc/lpc.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,8 +18,8 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_LPC_H_
-#define _BAYTRAIL_LPC_H_
+#ifndef _SOC_LPC_H_
+#define _SOC_LPC_H_
/* PCI config registers in LPC bridge. */
#define REVID 0x08
@@ -37,7 +38,7 @@
#define RID_A_STEPPING_START 1
#define RID_B_STEPPING_START 5
#define RID_C_STEPPING_START 0xe
-enum baytrail_stepping {
+enum soc_stepping {
STEP_A0,
STEP_A1,
STEP_B0,
@@ -51,4 +52,4 @@ enum baytrail_stepping {
#define GCS 0x00
# define BILD (1 << 0)
-#endif /* _BAYTRAIL_LPC_H_ */
+#endif /* _SOC_LPC_H_ */
diff --git a/src/soc/intel/braswell/include/soc/mrc_wrapper.h b/src/soc/intel/braswell/include/soc/mrc_wrapper.h
deleted file mode 100644
index 355dce0..0000000
--- a/src/soc/intel/braswell/include/soc/mrc_wrapper.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * MRC wrapper definitions
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Google Inc. nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _MRC_WRAPPER_H_
-#define _MRC_WRAPPER_H_
-
-#define MRC_PARAMS_VER 5
-
-#define NUM_CHANNELS 2
-
-/* Provide generic x86 calling conventions. */
-#define ABI_X86 __attribute((regparm(0)))
-
-enum {
- DRAM_INFO_SPD_SMBUS, /* Use the typical SPD smbus access. */
- DRAM_INFO_SPD_MEM, /* SPD info in memory. */
- DRAM_INFO_DETAILED, /* Timing info not in SPD format. */
-};
-
-enum dram_type {
- DRAM_DDR3,
- DRAM_DDR3L,
- DRAM_LPDDR3,
-};
-
-/* Errors returned by the MRC wrapper. */
-enum mrc_wrapper_error {
- INVALID_VER = -1,
- INVALID_DRAM_TYPE = -2,
- INVALID_SLEEP_MODE = -3,
- PLATFORM_SETTINGS_FAIL = -4,
- DIMM_DETECTION_FAILURE = -5,
- MEMORY_CONFIG_FAILURE = -6,
- INVALID_CPU_ODT_SETTING = -7,
- INVALID_DRAM_ODT_SETTING = -8,
-};
-
-struct mrc_mainboard_params {
- int dram_type;
- int dram_info_location; /* DRAM_INFO_* */
- int dram_is_slotted; /* mobo has DRAM slots. */
- /*
- * The below ODT settings are only honored when !dram_is_slotted.
- * Additionally, weaker_odt_settings being non-zero causes
- * cpu_odt_value to not be honored as weaker_odt_settings have a
- * special training path.
- */
- int weaker_odt_settings;
- /* Allowed settings: 60, 80, 100, 120, and 150. */
- int cpu_odt_value;
- /* Allowed settings: 60 and 120. */
- int dram_odt_value;
- int spd_addrs[NUM_CHANNELS];
- void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */
-} __attribute__((packed));
-
-struct mrc_params {
- /* Mainboard Inputs */
- int version;
-
- struct mrc_mainboard_params mainboard;
-
- void ABI_X86 (*console_out)(unsigned char byte);
-
- int prev_sleep_state;
-
- int saved_data_size;
- const void *saved_data;
-
- int txe_size_mb; /* TXE memory size in megabytes. */
- int rmt_enabled; /* Enable RMT training + prints. */
- int io_hole_mb; /* Size of IO hole in MiB. */
-
- /* Outputs */
- void *txe_base_address;
- int data_to_save_size;
- void *data_to_save;
-} __attribute__((packed));
-
-/* Call into wrapper. */
-typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *);
-
-#endif /* _MRC_WRAPPER_H_ */
diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 668eebf..7426629 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -2,13 +2,14 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
@@ -17,17 +18,18 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_MSR_H_
-#define _BAYTRAIL_MSR_H_
+#ifndef _SOC_MSR_H_
+#define _SOC_MSR_H_
#define MSR_IA32_PLATFORM_ID 0x17
+#define MSR_IA32_BIOS_SIGN_ID 0x8B
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd
#define MSR_PLATFORM_INFO 0xce
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
-#define SINGLE_PCTL (1 << 11)
+#define SINGLE_PCTL (1 << 11)
#define MSR_POWER_MISC 0x120
-#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
-#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
+#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
+#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
#define MSR_IA32_PERF_CTL 0x199
#define MSR_IA32_MISC_ENABLES 0x1a0
#define MSR_POWER_CTL 0x1fc
@@ -45,7 +47,6 @@
#define MSR_CPU_THERM_CFG2 0x674
#define MSR_CPU_THERM_SENS_CFG 0x675
-/* Read BCLK from MSR */
-unsigned bus_freq_khz(void);
+#define BUS_FREQ_KHZ 100000 /* 100 MHz */
-#endif /* _BAYTRAIL_MSR_H_ */
+#endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 9304c4a..1c25cb2 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,8 +19,8 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_NVS_H_
-#define _BAYTRAIL_NVS_H_
+#ifndef _SOC_NVS_H_
+#define _SOC_NVS_H_
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
@@ -39,12 +40,13 @@ typedef struct {
u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
u8 lids; /* 0x0f - LID state (open = 1) */
u8 pwrs; /* 0x10 - Power state (AC = 1) */
- u8 pcnt; /* 0x11 - Processor Count */
+ u8 pcnt; /* 0x11 - Processor Count */
u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */
- u8 rsvd1[7];
+ u8 bdid; /* 0x19 - Board ID */
+ u8 rsvd1[6];
/* Device Config */
u8 s5u0; /* 0x20 - Enable USB0 in S5 */
@@ -58,21 +60,22 @@ typedef struct {
u8 rsvd2[8];
/* Base Addresses */
- u32 obsolete_cmem; /* 0x30 - CBMEM TOC */
+ u32 cmem; /* 0x30 - CBMEM TOC */
u32 tolm; /* 0x34 - Top of Low Memory */
u32 cbmc; /* 0x38 - coreboot memconsole */
u8 rsvd3[196];
- /* ChromeOS specific (0x100-0xfff)*/
+ /* ChromeOS specific (0x100-0xfff) */
chromeos_acpi_t chromeos;
- /* Baytrail LPSS (0x1000) */
+ /* LPSS (0x1000) */
device_nvs_t dev;
} __attribute__((packed)) global_nvs_t;
+void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
#endif
-#endif /* _BAYTRAIL_NVS_H_ */
+#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h
index 852de40..6328dfe 100644
--- a/src/soc/intel/braswell/include/soc/pattrs.h
+++ b/src/soc/intel/braswell/include/soc/pattrs.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,8 +18,8 @@
* Foundation, Inc.
*/
-#ifndef _PATTRS_H_
-#define _PATTRS_H_
+#ifndef _SOC_PATTRS_H_
+#define _SOC_PATTRS_H_
#include <stdint.h>
#include <cpu/x86/msr.h>
@@ -31,7 +32,8 @@ enum {
IACORE_END
};
-/* The pattrs structure is a common place to stash pertinent information
+/*
+ * The pattrs structure is a common place to stash pertinent information
* about the processor or platform. Instead of going to the source (msrs, cpuid)
* every time an attribute is needed use the pattrs structure.
*/
@@ -49,16 +51,14 @@ struct pattrs {
unsigned bclk_khz;
};
-/* This is just to hide the abstraction w/o relying on how the underlying
- * storage is allocated. */
-#define PATTRS_GLOB_NAME __global_pattrs
-#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME
-extern DEFINE_PATTRS;
-
+/*
+ * This is just to hide the abstraction w/o relying on how the underlying
+ * storage is allocated.
+ */
+extern struct pattrs __global_pattrs;
static inline const struct pattrs *pattrs_get(void)
{
- return &PATTRS_GLOB_NAME;
+ return &__global_pattrs;
}
-
-#endif /* _PATTRS_H_ */
+#endif /* _SOC_PATTRS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h
index bb75f34..5594675 100644
--- a/src/soc/intel/braswell/include/soc/pci_devs.h
+++ b/src/soc/intel/braswell/include/soc/pci_devs.h
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,139 +18,137 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_PCI_DEVS_H_
-#define _BAYTRAIL_PCI_DEVS_H_
+#ifndef _SOC_PCI_DEVS_H_
+#define _SOC_PCI_DEVS_H_
/* All these devices live on bus 0 with the associated device and function */
/* SoC transaction router */
#define SOC_DEV 0x0
#define SOC_FUNC 0
-# define SOC_DEVID 0x0f00
+# define SOC_DEVID 0x2280
/* Graphics and Display */
#define GFX_DEV 0x2
#define GFX_FUNC 0
-# define GFX_DEVID 0x0f31
+# define GFX_DEVID 0x22b1
+
+/* MMC Port */
+#define MMC_DEV 0x10
+#define MMC_FUNC 0
+# define MMC_DEVID 0x2294
/* SDIO Port */
#define SDIO_DEV 0x11
#define SDIO_FUNC 0
-# define SDIO_DEVID 0x0f15
+# define SDIO_DEVID 0x2295
/* SD Port */
#define SD_DEV 0x12
#define SD_FUNC 0
-# define SD_DEVID 0x0f16
+# define SD_DEVID 0x2296
/* SATA */
#define SATA_DEV 0x13
#define SATA_FUNC 0
-#define IDE1_DEVID 0x0f20
-#define IDE2_DEVID 0x0f21
-#define AHCI1_DEVID 0x0f22
-#define AHCI2_DEVID 0x0f23
+#define AHCI1_DEVID 0x22a3
/* xHCI */
#define XHCI_DEV 0x14
#define XHCI_FUNC 0
-# define XHCI_DEVID 0x0f35
+#define XHCI_DEVID 0x22b5
/* LPE Audio */
#define LPE_DEV 0x15
#define LPE_FUNC 0
-# define LPE_DEVID 0x0f28
-
-/* MMC Port */
-#define MMC_DEV 0x17
-#define MMC_FUNC 0
-# define MMC_DEVID 0x0f50
+# define LPE_DEVID 0x22a8
/* Serial IO 1 */
#define SIO1_DEV 0x18
# define SIO_DMA1_DEV SIO1_DEV
# define SIO_DMA1_FUNC 0
-# define SIO_DMA1_DEVID 0x0f40
+# define SIO_DMA1_DEVID 0x22c0
# define I2C1_DEV SIO1_DEV
# define I2C1_FUNC 1
-# define I2C1_DEVID 0x0f41
+# define I2C1_DEVID 0x22c1
# define I2C2_DEV SIO1_DEV
# define I2C2_FUNC 2
-# define I2C2_DEVID 0x0f42
+# define I2C2_DEVID 0x22c2
# define I2C3_DEV SIO1_DEV
# define I2C3_FUNC 3
-# define I2C3_DEVID 0x0f43
+# define I2C3_DEVID 0x22c3
# define I2C4_DEV SIO1_DEV
# define I2C4_FUNC 4
-# define I2C4_DEVID 0x0f44
+# define I2C4_DEVID 0x22c4
# define I2C5_DEV SIO1_DEV
# define I2C5_FUNC 5
-# define I2C5_DEVID 0x0f45
+# define I2C5_DEVID 0x22c5
# define I2C6_DEV SIO1_DEV
# define I2C6_FUNC 6
-# define I2C6_DEVID 0x0f46
+# define I2C6_DEVID 0x22c6
# define I2C7_DEV SIO1_DEV
# define I2C7_FUNC 7
-# define I2C7_DEVID 0x0f47
+# define I2C7_DEVID 0x22c7
/* Trusted Execution Engine */
#define TXE_DEV 0x1a
#define TXE_FUNC 0
-# define TXE_DEVID 0x0f18
+# define TXE_DEVID 0x2298
/* HD Audio */
#define HDA_DEV 0x1b
#define HDA_FUNC 0
-# define HDA_DEVID 0x0f04
+# define HDA_DEVID 0x2284
/* PCIe Ports */
#define PCIE_DEV 0x1c
# define PCIE_PORT1_DEV PCIE_DEV
# define PCIE_PORT1_FUNC 0
-# define PCIE_PORT1_DEVID 0x0f48
+# define PCIE_PORT1_DEVID 0x22c8
# define PCIE_PORT2_DEV PCIE_DEV
# define PCIE_PORT2_FUNC 1
-# define PCIE_PORT2_DEVID 0x0f4a
+# define PCIE_PORT2_DEVID 0x22ca
# define PCIE_PORT3_DEV PCIE_DEV
# define PCIE_PORT3_FUNC 2
-# define PCIE_PORT3_DEVID 0x0f4c
+# define PCIE_PORT3_DEVID 0x22cc
# define PCIE_PORT4_DEV PCIE_DEV
# define PCIE_PORT4_FUNC 3
-# define PCIE_PORT4_DEVID 0x0f4e
-
-/* EHCI */
-#define EHCI_DEV 0x1d
-#define EHCI_FUNC 0
-# define EHCI_DEVID 0x0f34
+# define PCIE_PORT4_DEVID 0x22ce
+/* Total number of ROOT PORTS */
+#define MAX_ROOT_PORTS_BSW 4
/* Serial IO 2 */
#define SIO2_DEV 0x1e
# define SIO_DMA2_DEV SIO2_DEV
# define SIO_DMA2_FUNC 0
-# define SIO_DMA2_DEVID 0x0f06
+# define SIO_DMA2_DEVID 0x2286
# define PWM1_DEV SIO2_DEV
# define PWM1_FUNC 1
-# define PWM1_DEVID 0x0f08
+# define PWM1_DEVID 0x2288
# define PWM2_DEV SIO2_DEV
# define PWM2_FUNC 2
-# define PWM2_DEVID 0x0f09
+# define PWM2_DEVID 0x2289
# define HSUART1_DEV SIO2_DEV
# define HSUART1_FUNC 3
-# define HSUART1_DEVID 0x0f0a
+# define HSUART1_DEVID 0x228a
# define HSUART2_DEV SIO2_DEV
# define HSUART2_FUNC 4
-# define HSUART2_DEVID 0x0f0c
+# define HSUART2_DEVID 0x228c
# define SPI_DEV SIO2_DEV
# define SPI_FUNC 5
-# define SPI_DEVID 0xf0e
+# define SPI_DEVID 0x228e
/* Platform Controller Unit */
#define PCU_DEV 0x1f
# define LPC_DEV PCU_DEV
# define LPC_FUNC 0
-# define LPC_DEVID 0x0f1c
+# define LPC_DEVID 0x229c
# define SMBUS_DEV PCU_DEV
# define SMBUS_FUNC 3
# define SMBUS_DEVID 0x0f12
-#endif /* _BAYTRAIL_PCI_DEVS_H_ */
+/* PCH SCC Device Modes */
+#define PCH_DISABLED 0
+#define PCH_PCI_MODE 1
+#define PCH_ACPI_MODE 2
+#endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h
index dd0b90d..9307d9b 100644
--- a/src/soc/intel/braswell/include/soc/pcie.h
+++ b/src/soc/intel/braswell/include/soc/pcie.h
@@ -2,13 +2,14 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
@@ -17,8 +18,8 @@
* Foundation, Inc.
*/
-#ifndef _BAYTRAIL_PCIE_H_
-#define _BAYTRAIL_PCIE_H_
+#ifndef _SOC_PCIE_H_
+#define _SOC_PCIE_H_
/* PCIe root port config space registers. */
#define XCAP 0x40
@@ -98,5 +99,4 @@
#define PHYCTL4 0x408
# define SQDIS (1 << 27)
-#define PCIE_ROOT_PORT_COUNT 4
-#endif /* _BAYTRAIL_PCIE_H_ */
+#endif /* _SOC_PCIE_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h
new file mode 100644
index 0000000..d9e5a67
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/pei_data.h
@@ -0,0 +1,62 @@
+/*
+ * Broadwell UEFI PEI wrapper
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PEI_DATA_H_
+#define _PEI_DATA_H_
+
+#include <types.h>
+
+#define PEI_VERSION 22
+
+#define ABI_X86 __attribute__((regparm(0)))
+
+typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
+
+struct pei_data {
+ /* Chip settings */
+ void *spd_data_ch0;
+ void *spd_data_ch1;
+ uint8_t spd_ch0_config;
+ uint8_t spd_ch1_config;
+
+ /* System state information */
+ int boot_mode;
+
+ /* Fast boot and S3 resume MRC data */
+ int saved_data_size;
+ const void *saved_data;
+ int disable_saved_data;
+
+ /* New save data from MRC */
+ int data_to_save_size;
+ void *data_to_save;
+};
+
+typedef struct pei_data PEI_DATA;
+
+#endif /* _PEI_DATA_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/soc/intel/braswell/include/soc/pei_wrapper.h
new file mode 100644
index 0000000..59f2bb3
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/pei_wrapper.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _SOC_PEI_WRAPPER_H_
+#define _SOC_PEI_WRAPPER_H_
+
+#include <soc/pei_data.h>
+
+typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
+
+void broadwell_fill_pei_data(struct pei_data *pei_data);
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+
+#endif
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
new file mode 100644
index 0000000..ca06819
--- /dev/null
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -0,0 +1,267 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+
+#define IOCOM1 0x3f8
+
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
+#define PRSTS 0x00
+# define PMC_WDT_STS (1 << 15)
+# define SEC_GBLRST_STS (1 << 7)
+# define SEC_WDT_STS (1 << 6)
+# define WOL_OVR_WK_STS (1 << 5)
+# define PMC_WAKE_STS (1 << 4)
+#define PMC_CFG 0x08
+# define SPS (1 << 5)
+# define NO_REBOOT (1 << 4)
+# define SX_ENT_TO_EN (1 << 3)
+# define TIMING_T581_SHIFT (0)
+# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT)
+# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT)
+# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT)
+# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT)
+# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT)
+#define VLV_PM_STS 0x0c
+# define PMC_MSG_FULL_STS (1 << 24)
+# define PMC_MSG_4_FULL_STS (1 << 23)
+# define PMC_MSG_3_FULL_STS (1 << 22)
+# define PMC_MSG_2_FULL_STS (1 << 21)
+# define PMC_MSG_1_FULL_STS (1 << 20)
+# define CODE_REQ (1 << 8)
+# define HPR_ENT_TO (1 << 2)
+# define SX_ENT_TO (1 << 1)
+#define GEN_PMCON1 0x20
+# define UART_EN (1 << 24)
+# define DISB (1 << 23)
+# define MEM_SR (1 << 21)
+# define SRS (1 << 20)
+# define CTS (1 << 19)
+# define MS4V (1 << 18)
+# define PWR_FLR (1 << 16)
+# define PME_B0_S5_DIS (1 << 15)
+# define SUS_PWR_FLR (1 << 14)
+# define WOL_EN_OVRD (1 << 13)
+# define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
+# define GEN_RST_STS (1 << 9)
+# define RPS (1 << 2)
+# define AFTERG3_EN (1 << 0)
+#define GEN_PMCON2 0x24
+# define SLPSX_STR_POL_LOCK (1 << 18)
+# define BIOS_PCI_EXP_EN (1 << 10)
+# define PWRBTN_LVL (1 << 9)
+# define SMI_LOCK (1 << 4)
+#define ETR 0x48
+# define CF9LOCK (1 << 31)
+# define LTR_DEF (1 << 22)
+# define IGNORE_HPET (1 << 21)
+# define CF9GR (1 << 20)
+# define CWORWRE (1 << 18)
+#define FUNC_DIS 0x34
+# define SIO_DMA2_DIS (1 << 0)
+# define PWM1_DIS (1 << 1)
+# define PWM2_DIS (1 << 2)
+# define HSUART1_DIS (1 << 3)
+# define HSUART2_DIS (1 << 4)
+# define SPI_DIS (1 << 5)
+# define SDIO_DIS (1 << 9)
+# define SD_DIS (1 << 10)
+# define MMC_DIS (1 << 11)
+# define HDA_DIS (1 << 12)
+# define LPE_DIS (1 << 13)
+# define OTG_DIS (1 << 14)
+# define XHCI_DIS (1 << 15)
+# define SATA_DIS (1 << 17)
+# define EHCI_DIS (1 << 18)
+# define TXE_DIS (1 << 19)
+# define PCIE_PORT1_DIS (1 << 20)
+# define PCIE_PORT2_DIS (1 << 21)
+# define PCIE_PORT3_DIS (1 << 22)
+# define PCIE_PORT4_DIS (1 << 23)
+# define SIO_DMA1_DIS (1 << 24)
+# define I2C1_DIS (1 << 25)
+# define I2C2_DIS (1 << 26)
+# define I2C3_DIS (1 << 27)
+# define I2C4_DIS (1 << 28)
+# define I2C5_DIS (1 << 29)
+# define I2C6_DIS (1 << 30)
+# define I2C7_DIS (1 << 31)
+#define FUNC_DIS2 0x38
+# define USH_SS_PHY_DIS (1 << 2)
+# define OTG_SS_PHY_DIS (1 << 1)
+# define SMBUS_DIS (1 << 0)
+#define GPIO_ROUT 0x58
+# define ROUTE_MASK 3
+# define ROUTE_NONE 0
+# define ROUTE_SMI 1
+# define ROUTE_SCI 2
+#define PLT_CLK_CTL_0 0x60
+#define PLT_CLK_CTL_1 0x64
+#define PLT_CLK_CTL_2 0x68
+#define PLT_CLK_CTL_3 0x6c
+#define PLT_CLK_CTL_4 0x70
+#define PLT_CLK_CTL_5 0x74
+# define CLK_FREQ_25MHZ (0x0 << 2)
+# define CLK_FREQ_19P2MHZ (0x1 << 2)
+# define CLK_CTL_D3_LPE (0x0 << 0)
+# define CLK_CTL_ON (0x1 << 0)
+# define CLK_CTL_OFF (0x2 << 0)
+#define PME_STS 0xc0
+#define GPE_LEVEL_EDGE 0xc4
+# define GPE_EDGE 0
+# define GPE_LEVEL 1
+#define GPE_POLARITY 0xc8
+# define GPE_ACTIVE_HIGH 1
+# define GPE_ACTIVE_LOW 0
+#define LOCK 0xcc
+
+/* IO Mapped registers behind ACPI_BASE_ADDRESS */
+#define PM1_STS 0x00
+#define WAK_STS (1 << 15)
+#define PCIEXPWAK_STS (1 << 14)
+#define USB_STS (1 << 13)
+#define PRBTNOR_STS (1 << 11)
+#define RTC_STS (1 << 10)
+#define PWRBTN_STS (1 << 8)
+#define GBL_STS (1 << 5)
+#define TMROF_STS (1 << 0)
+#define PM1_EN 0x02
+#define PCIEXPWAK_DIS (1 << 14)
+#define USB_WAKE_EN (1 << 13)
+#define RTC_EN (1 << 10)
+#define PWRBTN_EN (1 << 8)
+#define GBL_EN (1 << 5)
+#define TMROF_EN (1 << 0)
+#define PM1_CNT 0x04
+#define SLP_EN (1 << 13)
+#define SLP_TYP_SHIFT 10
+#define SLP_TYP (7 << SLP_TYP_SHIFT)
+#define SLP_TYP_S0 0
+#define SLP_TYP_S1 1
+#define SLP_TYP_S3 5
+#define SLP_TYP_S4 6
+#define SLP_TYP_S5 7
+#define GBL_RLS (1 << 2)
+#define BM_RLD (1 << 1)
+#define SCI_EN (1 << 0)
+#define PM1_TMR 0x08
+#define GPE0_STS 0x20
+#define GPE0_EN 0x28
+#define SUS_GPIO_EN7_BIT 23
+#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT)
+#define SUS_GPIO_EN6_BIT 22
+#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT)
+#define SUS_GPIO_EN5_BIT 21
+#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT)
+#define SUS_GPIO_EN4_BIT 20
+#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT)
+#define SUS_GPIO_EN3_BIT 19
+#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT)
+#define SUS_GPIO_EN2_BIT 18
+#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT)
+#define SUS_GPIO_EN1_BIT 17
+#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT)
+#define SUS_GPIO_EN0_BIT 16
+#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT)
+#define SUS_GPIO_STS0 (1 << 16)
+#define PCIE_WAKE3_STS (1 << 8)
+#define PCIE_WAKE2_STS (1 << 7)
+#define PCIE_WAKE1_STS (1 << 6)
+#define PCIE_WAKE0_STS (1 << 3)
+#define PCI_EXP_STS (1 << 9)
+#define PME_B0_EN (1 << 13)
+#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT
+#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x)
+#define SMI_EN 0x30
+#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
+#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */
+#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
+#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
+#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
+#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
+#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
+#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */
+#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
+#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
+#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
+#define SMI_STS 0x34
+#define ALT_GPIO_SMI 0x38
+#define UPRWC 0x3c
+# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
+#define GPE_CTRL 0x40
+#define PM2A_CNT_BLK 0x50
+#define TCO_RLD 0x60
+#define TCO_STS 0x64
+# define SECOND_TO_STS (1 << 17)
+# define TCO_TIMEOUT (1 << 3)
+#define TCO1_CNT 0x68
+# define TCO_LOCK (1 << 12)
+# define TCO_TMR_HALT (1 << 11)
+#define TCO_TMR 0x70
+
+/* Generic sleep state types */
+#define SLEEP_STATE_S0 0
+#define SLEEP_STATE_S3 3
+#define SLEEP_STATE_S5 5
+
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+
+/* Track power state from reset to log events. */
+struct chipset_power_state {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+ uint32_t pm1_cnt;
+ uint32_t gpe0_sts;
+ uint32_t gpe0_en;
+ uint32_t tco_sts;
+ uint32_t prsts;
+ uint32_t gen_pmcon1;
+ uint32_t gen_pmcon2;
+ int prev_sleep_state;
+} __attribute__((packed));
+
+/* Power Management Utility Functions. */
+uint16_t get_pmbase(void);
+uint32_t clear_smi_status(void);
+uint16_t clear_pm1_status(void);
+uint32_t clear_tco_status(void);
+uint32_t clear_gpe_status(void);
+uint32_t clear_alt_status(void);
+void clear_pmc_status(void);
+void enable_smi(uint32_t mask);
+void disable_smi(uint32_t mask);
+void enable_pm1(uint16_t events);
+void enable_pm1_control(uint32_t mask);
+void disable_pm1_control(u
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