[coreboot-gerrit] Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Sun Oct 18 11:51:22 CEST 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12008
-gerrit
commit 05960e88ca9f3fe4a3a9f97ca30cab05e27ba975
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Fri Jun 26 00:17:10 2015 -0500
northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 ++++++++
src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 16 ++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index b2dd315..0ee945c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -5815,7 +5815,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct)
{
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
mct_ProgramODT_D(pMCTstat, pDCTstat, dct);
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
@@ -5825,6 +5829,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
u32 dword;
u32 dev = pDCTstat->dev_dct;
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
/* FIXME
* Mainboards need to be able to specify the maximum number of DIMMs installable per channel
* For now assume a maximum of 2 DIMMs per channel can be installed
@@ -6139,6 +6145,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2);
}
}
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat,
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 51cbf16..380c5f2 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -192,9 +192,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct)
u32 dev = pDCTstat->dev_dct;
u32 val;
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
do {
val = Get_NB32_DCT(dev, dct, 0x98);
} while (!(val & (1 << DctAccessDone)));
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct)
@@ -239,6 +243,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
u32 dev = pDCTstat->dev_dct;
u32 val;
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
val = Get_NB32_DCT(dev, dct, 0x7c);
val &= ~0x00ffffff;
val |= EMRS;
@@ -248,6 +254,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS)
do {
val = Get_NB32_DCT(dev, dct, 0x7c);
} while (val & (1 << SendMrsCmd));
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
static u32 mct_MR2(struct MCTStatStruc *pMCTstat,
@@ -557,6 +565,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
u32 dev = pDCTstat->dev_dct;
u32 dword;
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
/*1.Program MrsAddress[10]=1
2.Set SendZQCmd=1
*/
@@ -573,6 +583,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
/* 4.Wait 512 MEMCLKs */
mct_Wait(300);
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
@@ -582,6 +594,8 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
u32 dword;
u32 dev = pDCTstat->dev_dct;
+ printk(BIOS_DEBUG, "%s: Start\n", __func__);
+
if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) {
/* 3.Program F2x[1,0]7C[EnDramInit]=1 */
dword = Get_NB32_DCT(dev, dct, 0x7c);
@@ -663,4 +677,6 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x7C, dword);
mct_DCTAccessDone(pDCTstat, dct);
}
+
+ printk(BIOS_DEBUG, "%s: Done\n", __func__);
}
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