[coreboot-gerrit] Patch set updated for coreboot: cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage
Timothy Pearson (tpearson@raptorengineeringinc.com)
gerrit at coreboot.org
Thu Oct 29 15:51:57 CET 2015
Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12250
-gerrit
commit 91e3c0e8ae648f21e564a2a3f62a1d8377c5fdcb
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date: Thu Oct 29 01:33:25 2015 -0500
cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage
This mirrors a similar commit made to Family 10h support
in changeset 11966 file model_10xxx_init.c
TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222
Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834
Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
src/cpu/amd/model_fxx/model_fxx_init.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index db936f8..93fa07f 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -460,6 +460,18 @@ static void model_fxx_init(device_t dev)
/* Turn on caching if we haven't already */
x86_enable_cache();
+
+ /* Initialize all variable MTRRs except the first pair */
+ msr.hi = 0x00000000;
+ msr.lo = 0x00000000;
+
+ disable_cache();
+
+ for (i = 0x2; i < 0x10; i++) {
+ wrmsr(0x00000200 | i, msr);
+ }
+
+ enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
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