[coreboot-gerrit] Patch set updated for coreboot: fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8485

-gerrit

commit f644a4dbbd823c8a48bde75b71f67429f93b9b5b
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Wed Feb 18 14:51:41 2015 -0600

    fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
    
    POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
    mess of it, by forcing a build-time error when CONFIG_POST_IO was not
    being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
    
    Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
    "select POST_IO" from boards that have it.
    
    Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
---
 src/drivers/intel/fsp1_0/cache_as_ram.inc  | 18 +++++-------------
 src/mainboard/intel/bakersport_fsp/Kconfig |  1 -
 src/mainboard/intel/bayleybay_fsp/Kconfig  |  1 -
 src/mainboard/intel/minnowmax/Kconfig      |  4 ----
 src/mainboard/intel/mohonpeak/Kconfig      |  1 -
 5 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc
index cdbda54..32da60f8 100644
--- a/src/drivers/intel/fsp1_0/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc
@@ -29,16 +29,6 @@
 # error "CONFIG_FSP_LOC must be set."
 #endif
 
-#ifndef CONFIG_POST_IO
-# error "CONFIG_POST_IO must be set."
-#endif
-
-#if CONFIG_POST_IO
-# ifndef CONFIG_POST_IO_PORT
-#  error "CONFIG_POST_IO_PORT must be set."
-# endif
-#endif
-
 #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC
 # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set."
 #endif
@@ -145,11 +135,13 @@ halt2:
 	movb  $0xBB, %ah
 
 .Lhlt:
+	/*
+	 * Here, we show a 16-bit POST code. %al is the return value from the
+	 * FSP blob, and %ah is an indicator of where we came from.
+	 */
 	xchg  %al, %ah
-#if CONFIG_POST_IO
+#if IS_ENABLED(CONFIG_POST_IO)
 	outb  %al, $CONFIG_POST_IO_PORT
-#else
-	post_code(POST_DEAD_CODE)
 #endif
 	movl  $LHLT_DELAY, %ecx
 .Lhlt_Delay:
diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig
index c382bac..c42f7fc 100644
--- a/src/mainboard/intel/bakersport_fsp/Kconfig
+++ b/src/mainboard/intel/bakersport_fsp/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
-	select POST_IO
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select TSC_MONOTONIC_TIMER
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index a5c7605..e4a5ace 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
-	select POST_IO
 	select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 	select TSC_MONOTONIC_TIMER
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
index 636972f..c3265d7 100644
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -68,10 +68,6 @@ config VIRTUAL_ROM_SIZE
 	depends on ENABLE_FSP_FAST_BOOT
 	default 0x800000
 
-config POST_IO
-	bool
-	default n
-
 config POST_DEVICE
 	bool
 	default n
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
index 996cea2..0085da4 100644
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ b/src/mainboard/intel/mohonpeak/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
 	select MMCONF_SUPPORT
-	select POST_IO
 	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
 
 config MAINBOARD_DIR